XR17D158 Exar Corporation, XR17D158 Datasheet - Page 25

• Manufacturer Part Number: XR17D158
• Description: Eight-channel Pci-bus Uart
• Manufacturer: Exar Corporation

XR17D158
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
REV. P1.0.0
The transmit and receive data registers are defined for channel 0 to channel 7 with each channel having it’s
own address as shown in
receive and transmit data registers in more detail.
Each Channel Normal Receive Data FIFO Address for channels 0 to 7 are at 0x0100, 0x0300, 0x0500,
0x0700, 0x0900, 0x0B000, 0x0D00 and 0x0F00.
Each Channel Normal Transmit Data FIFO Address for Channel 0 to 7 are at 0x0100, 0x0300, 0x0500, 0x0700,
0x0900, 0x0B00, 0x0D00 and 0x0F00.
Each Channel Special Receive FIFO Data Address for channel 0 to 7 are at 0x0180 0x-380, 0x0580, 0x0780,
0x0980, 0x0B80, 0x0D80 and 0x0F80. The Status and Data bytes must be read in 16 or 32 bits format to
maintain data integrity. Please see the programming examples on how to use the Special Receive FIFO feature
on
4.1
Data Bit-31
WITH N
Data Bit-31
page
PCI Bus
Read n+0 to n+3
Read n+4 to n+7
Write n+0 to n+3
Write n+4 to n+7
W
R
PCI Bus
B 7
EAD
B 7
RITE
FIFO DATA LOADING AND UNLOADING THROUGH THE DEVICE CONFIGURATION REGISTERS
IN 32-BIT FORMAT.
B 6
Transmit Data Byte n+3
B 6
53.
Etc.
Etc.
RX FIFO,
Receive Data Byte n+3
O
TX FIFO
B 5
E
B 5
RRORS
B 4
B 4
B 3
B 3
B 2
B 2
Channel 0 to 7 Transmit Data in 32-bit alignment through the Configuration Register Address
Channel 0 to 7 ReceiveData in 32-bit alignment through the Configuration Register Address
B 1
B 1
FIFO Data n+3
FIFO Data n+7
FIFO Data n+3
FIFO Data n+7
B 0
B 0
Table 2
B
B
0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00
0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00
B 7
YTE
B 7
YTE
B 6
B 6
Transmit Data Byte n+2
Receive Data Byte n+2
3
3
for faster loading and unloading. The following paragraphs illustrate the
B 5
B 5
B 4
B 4
B 3
B 3
B 2
B 2
FIFO Data n+2
FIFO Data n+6
FIFO Data n+2
FIFO Data n+6
B 1
B 1
B
B
B 0
B 0
YTE
YTE
25
B 7
B 7
2
2
B 6
B 6
Receive Data Byte n+1
Transmit Data Byte n+1
B 5
B 5
B 4
B 4
B 3
B 3
FIFO Data n+1
FIFO Data n+5
FIFO Data n+1
FIFO Data n+5
B 2
B 2
B
B
B 1
B 1
YTE
YTE
B 0
B 0
1
1
B 7
B 7
B 6
Receive Data Byte n+0
B 6
Transmit Data Byte n+0
PRELIMINARY
B 5
B 5
B 4
B 4
áç
áç
áç
áç
FIFO Data n+0
FIFO Data n+4
FIFO Data n+0
FIFO Data n+4
B 3
B 3
B
B
B 2
YTE
YTE
B 2
B 1
Data Bit-0
PCI Bus
B 1
0
0
Data Bit-0
PCI Bus
B 0
B 0