XR17D158 Exar Corporation, XR17D158 Datasheet - Page 26

• Manufacturer Part Number: XR17D158
• Description: Eight-channel Pci-bus Uart
• Manufacturer: Exar Corporation

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PRELIMINARY
The THR and RHR register address for channel 0 to channel 7 is shown in
for each channel 0 to 7 are located sequentially at address 0x0000, 0x0200, 0x0400, 0x0600, 0x0800,
0x0A000, 0x0C00 and 0x0E00. Transmit data byte is loaded to the THR when writing to that address and
receive data is unloaded from the RHR register when reading that address. Both THR and RHR registers are
16C550 compatible in 8-bit format, so each bus operation can only write or read in bytes.
4.2
Data Bit-31
WITH LSR
Read n+0 to n+1
Read n+2 to n+3
PCI Bus
R
EAD
B 7
FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR
AND RHR IN 8-BIT FORMAT.
B 6
Receive Data Byte n+1
RX FIFO,
Etc
B 5
E
T
ABLE
RRORS
B 4
B 3
C H 0
C H 2
C H 3
C H 3
C H 4
C H 5
C H 0
C H 1
C H 1
C H 2
C H 4
C H 5
C H 6
C H 7
8: T
C H 6
C H 7
Channel 0 to 7 Receive Data with Line Status Register in a 32-bit alignment through the Configuration
B 2
RANSMIT AND
0 x0 0 0 R e a d R H R
0 x4 0 0 R e a d R H R
0 x6 0 0 W rite T H R
0 x6 0 0 R e a d R H R
0 x8 0 0 R e a d R H R
TH R and R H R A dd ress Locations F or C H 0 to C H 7 (16C 550 C o m patib le)
0 xA 0 0 W rite T H R
0 xC 0 0 R e a d R H R
B 1
0 x0 0 0 W rite T H R
0 x2 0 0 W rite T H R
0 x2 0 0 R e a d R H R
0 x4 0 0 W rite T H R
0 x8 0 0 W rite T H R
0 xA 0 0 R e a d R H R
0 xE 0 0 R e a d R H R
0 xC 0 0 W rite T H R
Register Address 0x0180, 0x0380, 0x0580, 0x0780, 0x0980, 0x0B80, 0x0D80 and 0x0F80
0 xE 0 0 W rite T H R
FIFO Data n+1
FIFO Data n+3
B 0
B
B 7
YTE
B 6
Line Status Register n+1
3
R
B 5
ECEIVE
B 4
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B 3
D
ATA
B 2
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B 1
R
LSR n+1
LSR n+3
B
EGISTER IN
B 0
YTE
26
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
B 7
2
B 6
Receive Data Byte n+0
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B 5
B
YTE FORMAT
B 4
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B 3
FIFO Data n+0
FIFO Data n+2
B 2
B
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B 1
YTE
Table 8
, 16C550
B 0
1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B 7
below. The THR and RHR
B 6
Line Status Register n+0
COMPATIBLE
T H R R H R 1
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B 5
B 4
B 3
LSR n+0
LSR n+2
B
YTE
B 2
XR17D158
REV. P1.0.0
B 1
0
Data Bit-0
PCI Bus
B 0