XR17D158 Exar Corporation, XR17D158 Datasheet - Page 34

• Manufacturer Part Number: XR17D158
• Description: Eight-channel Pci-bus Uart
• Manufacturer: Exar Corporation

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PRELIMINARY
N
The transmitter section comprises of a 64 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an
8-bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO mode) or a data byte
from the FIFO when the FIFO is enabled by FCR bit-0. TSR shifts out every data bit with the 16X or 8X internal
clock. A bit time is 16 or 8 clock periods. The transmitter sends the start bit followed by the number of data bits,
inserts the proper parity bit if enable, and adds the stop bit(s). The status of the THR and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is also the
input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. A THR empty
interrupt can be generated when it is enabled in IER bit-1.
5.6
T
5.6.1
5.6.2
A
OTE
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 0
1 0 1 1
1 0 1 1
1 1 0 0
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
ABLE
A3-A0
DDRESS
: MCR bits 2 and 3 (OP1 and OP2 outputs) are not available in the XR17D158. They are present for 16C550
compatibility during Internal loopback, see
11: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
Transmitter
Transmit Holding Register (THR)
Transmitter Operation in non-FIFO
RXTRG
XCHAR
TXTRG
RXCNT
TXCNT
XOFF1
XOFF2
XON1
XON2
FCTR
N
MSR
MSR
SPR
EFR
R
AME
EG
W
R
R/W
R/W
R/W
EAD
RITE
W
W
W
W
W
W
W
R
R
R
R
/
Auto CTS/
RS485
Enable
DLY-3
B
Table
DSR
Bit-7
TRG
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-1
CD
IT
0
-7
Auto RTS/
RS485
Enable
DLY-2
B
Table
Bit-6
TRG
DTR
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-0
RI
IT
0
-6
Figure 13
Special
RS485
RS485
Enable
Select
DLY-1
B
DSR
Char
Bit-5
Auto
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
IT
0
-5
34
RS485 DLY-
MCR[7:5,2]
.
FCR[5:4],
IER [7:5],
ISR [5:4],
MSR[7:4]
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
RX Input
Invert IR
Enable
B
CTS
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
IT
0
0
-4
Reserved Reserved Reserved Reserved
RTS/DTR
Hyst Bit-3
Flow Cntl
Software
B
Delta
CD#
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
IT
0
-3
Hyst Bit-2
RTS/DTR
Flow Cntl
Software
B
Delta
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
RI#
IT
0
-2
S
HADED BITS ARE ENABLED BY
RTS/DTR
Hyst Bit-1
Flow Cntl
Software
Xon Det.
Indicator
DSR#
B
Delta
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
IT
-1
Hyst Bit-0
RTS/DTR
Flow Cntl
Software
Xoff Det.
Indicator
CTS#
B
Delta
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
IT
-0
XR17D158
REV. P1.0.0
EFR B
User Data
C
after read
Self-clear
OMMENT
IT
-4.