WM8978 Wolfson Microelectronics Ltd., WM8978 Datasheet - Page 78
Manufacturer Part Number
The WM8978 is a low power, high quality stereo codec designed for portable applications such as Digital still camera or Digital Camcorde
Wolfson Microelectronics Ltd.
RESETTING THE CHIP
Figure 42 2-Wire Serial Control Interface
RECOMMENDED POWER UP/DOWN SEQENCE
In 2-wire mode the WM8978 has a fixed device address, 0011010.
The WM8978 can be reset by performing a write of any value to the software reset register (address
0 hex). This will cause all register values to be reset to their default values. In addition to this there
is a Power-On Reset (POR) circuit which ensures that the registers are set to default when the
device is powered up.
The WM8978 can use up to five separate power supplies:
AVDD and AGND: Analogue supply, powers all analogue functions except the speaker output and
mono output drivers. AVDD can range from 2.5V to 3.6V and has the most significant impact on
overall power consumption (except for power consumed in the headphone). A large AVDD slightly
improves audio quality.
SPKVDD and SPKGND: Headphone and Speaker supplies, power the speaker and mono output
drivers. SPKVDD can range from 2.5V to 5V. SPKVDD can be tied to AVDD, but it requires separate
layout and decoupling capacitors to curb harmonic distortion. With a larger SPKVDD, louder
headphone and speaker outputs can be achieved with lower distortion. If SPKVDD is lower than
AVDD, the output signal may be clipped.
DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces.
DCVDD can range from 1.71V to 3.6V, and has no effect on audio quality. The return path for
DCVDD is DGND, which is shared with DBVDD.
DBVDD can range from 1.71V to 3.6V. DBVDD return path is through DGND.
It is possible to use the same supply voltage for all four supplies. However, digital and analogue
supplies should be routed and decoupled separately on the PCB to keep digital switching noise out
of the analogue signal paths.
DCVDD should be greater than or equal to 1.9V when using the PLL.
In order to minimise output ‘pop’ and ‘click’ noise it is recommended that the device is powered up in
a controlled sequence.
In addition to this it is recommended that the zero cross functions are used when changing the
volume in the PGAs.
RD / WR
register address and
CONTROL BYTE 1
1st register data bit
(BITS 15 TO 8)
CONTROL BYTE 1
remaining 8 bits of
(BITS 7 TO 0)
PTD Rev 2.6 November 2005
Preliminary Technical Data