AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 104

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Watchdog Timer
104
AT94K Series FPSLIC
Table 31. PWM Outputs OCR1X = $0000 or TOP
Notes:
In up/down PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances
from $0 000 . In overflow PW M mo de , the Timer O verflo w fla g is se t a s in norma l
Timer/Counter mode. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter
mode, i.e., it is executed when TOV1 is set provided that Timer Overflow Interrupt1 and global
interrupts are enabled. This also applies to the Timer Output Compare1 flags and interrupts.
The Watchdog Timer is clocked from a separate on-chip oscillator which runs at 1 MHz. This
is the typical value at V
els. By controlling the Watchdog Timer prescaler, the watchdog reset interval can be adjusted,
see Table 32 on page 105 for a detailed description. The WDR (watchdog reset) instruction
resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine
the reset period. If the reset period expires without another watchdog reset, the FPSLIC resets
and executes from the reset vector.
To prevent unintentional disabling of the watchdog, a special turn-off sequence must be fol-
lowed when the watchdog is disabled, see Figure 58.
Figure 58. Watchdog Timer
COM1X1
1. In overflow PWM mode, this table is only valid for OCR1X = TOP.
2. X = A or B
1
1
1
1
(2)
CC
= 3.3V. See characterization data for typical values at other V
COM1X0
0
0
1
1
(2)
OCR1X
(1)
$0000
$0000
TOP
TOP
(2)
Output OC1X
Rev. 1138F–FPSLI–06/02
H
H
L
L
(2)
CC
lev-