AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 137

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Slave Transmitter Mode
Miscellaneous States
Rev. 1138F–FPSLI–06/02
If the TWEA bit is reset during a transfer, the 2-wire Serial Interface will return a “Not Acknowl-
edged” (1) to SDA after the next received data byte. While TWEA is reset, the 2-wire Serial
Interface does not respond to its own Slave address. However, the 2-wire Serial Bus is still
monitored and address recognition may resume at any time by setting TWEA. This implies
that the TWEA bit may be used to temporarily isolate the 2-wire Serial Interface from the 2-
wire serial bus.
In ADC Noise Reduction Mode, Power-down Mode and Power-save Mode, the clock system
to the 2-wire Serial Interface is turned off. If the Slave Receiver mode is enabled, the interface
can still acknowledge a general call and its own Slave address by using the 2-wire serial bus
clock as a clock source. The part will then wake up from sleep and the 2-wire Serial Interface
will hold the SCL clock Low during the wake up and until the TWCINT flag is cleared.
Note that the 2-wire Serial Data Register – TWDR does not reflect the last byte present on the
bus when waking up from these Sleep Modes.
In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver
(see Figure 74). The transfer is initialized as in the Slave Receiver mode. When TWAR and
TWCR have been initialized, the 2-wire Serial Interface waits until it is addressed by its own
Slave address (or the general call address if enabled) followed by the data direction bit which
must be “1” (read) for the 2-wire Serial Interface to operate in the Slave Transmitter mode.
After its own Slave address and the read bit have been received, the 2-wire Serial Interrupt
flag is set and a valid status code can be read from TWSR. The status code is used to deter-
mine the appropriate software action. The appropriate action to be taken for each status code
is detailed in Table 43. The Slave Transmitter mode may also be entered if arbitration is lost
while the 2-wire Serial Interface is in the Master mode (see state $B0).
If the TWEA bit is reset during a transfer, the 2-wire Serial Interface will transmit the last byte
of the transfer and enter state $C0 or state $C8. the 2-wire Serial Interface is switched to the
not addressed Slave mode, and will ignore the Master if it continues the transfer. Thus the
Master Receiver receives all “1” as serial data. While TWEA is reset, the 2-wire Serial Inter-
face does not respond to its own Slave address. However, the 2-wire serial bus is still
monitored and address recognition may resume at any time by setting TWEA. This implies
that the TWEA bit may be used to temporarily isolate the 2-wire Serial Interface from the 2-
wire serial bus.
There are two status codes that do not correspond to a defined 2-wire Serial Interface state:
Status $F8 and Status $00, see Table 44.
Status $F8 indicates that no relevant information is available because the 2-wire Serial Inter-
rupt flag (TWINT) is not set yet. This occurs between other states, and when the 2-wire Serial
Interface is not involved in a serial transfer.
Status $00 indicates that a bus error has occurred during a 2-wire serial transfer. A bus error
occurs when a START or STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions are during the serial transfer of an address byte, a data byte
or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error,
the TWSTO flag must set and TWINT must be cleared by writing a logic 1 to it. This causes
the 2-wire Serial Interface to enter the not addressed Slave mode and to clear the TWSTO flag
(no other bits in TWCR are affected). The SDA and SCL lines are released and no STOP con-
dition is transmitted.
AT94K Series FPSLIC
137