AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 169

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

AC Timing Characteristics – 3.3V Operation
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: V
Minimum times based on best case: V
CMOS buffer delays are measured from a V
stant. Buffer delay is to a pad voltage of 1.5V with one output switching. Parameter based on characterization and
simulation; not tested in production. An FPGA power calculation is available in Atmel’s System Designer software (see also
page 160).
Rev. 1138F–FPSLI–06/02
Cell Function
Async RAM
Write
Write
Write
Write
Write
Write
Write
Write
Write/Read
Read
Read
Read
Sync RAM
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write/Read
Write/Read
Read
Read
Read
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WECYC
WEL
WEH
setup
hold
setup
hold
hold
PD
PD
PZX
PXZ
CYC
CLKL
CLKH
setup
hold
setup
hold
setup
hold
PD
PD
PD
PZX
PXZ
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
CC
CC
= 3.6V, temperature = 0°C
= 3.0V, temperature = 70°C
IH
Path
cycle time
we
we
wr addr setup-> we
wr addr hold -> we
din setup -> we
din hold -> we
oe hold -> we
din -> dout
rd addr -> dout
oe -> dout
oe -> dout
cycle time
clk
clk
we setup-> clk
we hold -> clk
wr addr setup-> clk
wr addr hold -> clk
wr data setup-> clk
wr data hold -> clk
din -> dout
clk -> dout
rd addr -> dout
oe -> dout
oe -> dout
of 1/2 V
CC
at the pad to the internal V
12.0
12.0
-25
5.0
5.0
5.3
0.0
5.0
0.0
0.0
8.7
6.3
2.9
3.5
5.0
5.0
3.2
0.0
5.0
0.0
3.9
0.0
8.7
5.8
6.3
2.9
3.5
AT94K Series FPSLIC
IH
Units
at A. The input buffer load is con-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
–
Pulse Width Low
Pulse Width High
–
–
rd addr = wr addr
–
–
Pulse Width High
–
–
–
rd addr = wr addr
rd addr = wr addr
–
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