AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 190
AT94K05AL
Manufacturer Part Number
AT94K05AL
Description
Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
Manufacturer
ATMEL Corporation
Datasheet
1.AT94K05AL.pdf
(192 pages)
Available stocks
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Part Number
Manufacturer
Quantity
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Part Number:
AT94K05AL-25DQI
Manufacturer:
ATMEL
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Table of Contents
1138F–FPSLI–06/02
Features................................................................................................. 1
Description ............................................................................................ 2
FPGA Core............................................................................................. 5
FPGA/AVR Interface and System Control ........................................ 21
Data SRAM .................................................................................................................. 22
by FPGA/AVR .............................................................................................................. 24
AVR Core and Peripherals ................................................................. 34
Y-register and
Z-register ...................................................................................................................... 44
Fast, Flexible and Efficient SRAM ........................................................................ 5
Fast, Efficient Array and Vector Multipliers ........................................................... 5
Cache Logic Design.............................................................................................. 5
Automatic Component Generators ....................................................................... 5
The Symmetrical Array ......................................................................................... 5
The Busing Network ............................................................................................. 6
Cell Connections................................................................................................... 8
The Cell ................................................................................................................ 8
RAM.................................................................................................................... 10
Clocking and Set/Reset ...................................................................................... 14
FPGA/AVR Interface– Memory-mapped Peripherals ......................................... 21
Program and
Data SRAM Access by FPGA – FPGAFrame Mode .......................................... 24
SRAM Access
AVR Cache Mode ............................................................................................... 29
Resets................................................................................................................. 29
System Control ................................................................................................... 30
Instruction Set Nomenclature (Summary)........................................................... 35
Complete Instruction Set Summary .................................................................... 36
Pin Descriptions.................................................................................................. 40
Clock Options ..................................................................................................... 41
Architectural Overview ........................................................................................ 42
General-purpose Register File............................................................................ 43
X-register,
ALU – Arithmetic Logic Unit................................................................................ 44
Multiplier Unit ...................................................................................................... 44
SRAM Data Memory........................................................................................... 44
Memory-mapped I/O ........................................................................................... 47
Software Control of System Configuration.......................................................... 51
FPGA Cache Logic ............................................................................................. 53
AT94K Series FPSLIC
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