AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 30

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

System Control
Configuration Modes
System Control
Register – FPGA/AVR
30
AT94K Series FPSLIC
The AT94K family has four configuration modes controlled by mode pins M0 and M2, see
Table 9.
Table 9. Configuration Modes
Modes 2 and 3 are reserved and are used for factory test.
Modes 0 and 1 are pin-compatible with the appropriate AT40K counterpart. AVR I/O will be
taken over by the configuration logic for the CHECK pin during both modes.
Refer to the “AT94K Series Configuration” application note for details on downloading
bitstreams.
The configuration control register in the FPSLIC consists of 8 bytes of data, which are loaded
with the FPGA/Prog. Code at power-up from external nonvolatile memory. FPSLIC System
Control Register values, see Table 10, can be set in the System Designer software. Recom-
mended defaults are included in the software.
Table 10. FPSLIC System Control Register
M2
0
0
1
1
Bit
SCR0 - SCR1
SCR2
SCR3
SCR4
SCR5
Description
Reserved
0 = Enable Cascading
1 = Disable Cascading
SCR2 controls the operation of the dual-function I/O CSOUT. When SCR2 is set,
the CSOUT pin is not used by the configuration during downloads, set this bit for
configurations where two or more devices are cascaded together. This applies for
configuration to another FPSLIC device or to an FPGA.
0 = Check Function Enabled
1 = Check Function Disabled
SCR3 controls the operation of the CHECK pin and enables the Check Function.
When SCR3 is set, the dual use AVR I/O/CHECK pin is not used by the
configuration during downloads, and can be used as AVR I/O.
0 = Memory Lockout Disabled
1 = Memory Lockout Enabled
SCR4 is the Security Flag and controls the writing and checking of configuration
memory during any subsequent configuration download. When SCR4 is set, any
subsequent configuration download initiated by the user, whether a normal
download or a CHECK function download, causes the INIT pin to immediately
activate. CON is released, and no further configuration activity takes place. The
download sequence during which SCR4 is set is NOT affected. The Control
Register write is also prohibited, so bit SCR4 may only be cleared by a power-on
reset or manual reset.
Reserved
M0
0
1
0
1
Name
Mode 0 - Master Serial
Mode 1 - Slave Serial Cascade
Mode 2 - Reserved
Mode 3 - Reserved
Rev. 1138F–FPSLI–06/02