AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 40

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Instruction Set Summary (Continued)
Pin Descriptions
V
GND
PortD (PD7..PD0)
PortE (PE7..PE0)
RX0
TX0
RX1
TX1
XTAL1
40
Mnemonics
CLS
SEV
CLV
SET
CLT
SEH
CLH
NOP
SLEEP
WDR
BREAK
CC
AT94K Series FPSLIC
Operands
Description
Clear Signed Test Flag
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
Clear T in SREG
Set Half-carry Flag in SREG
Clear Half-carry Flag in SREG
No Operation
Sleep
Watchdog Reset
Break
Supply voltage
Ground
Port D is an 8-bit bi-directional I/O port with internal programmable pull-up resistors. The Port
D output buffers can be programmed to sink/source either 6 or 20 mA (SCR54 – see “System
Control Register – FPGA/AVR” on page 30). As inputs, Port D pins that are externally pulled
Low will source current if the programmable pull-up resistors are activated.
The Port D pins are input with pull-up when a reset condition becomes active, even if the clock
is not running. On lower pin count packages Port D may not be available. Check the Pin List
for details.
Port E is an 8-bit bi-directional I/O port with internal programmable pull-up resistors. The Port
E output buffers can be programmed to sink/source either 6 or 20 mA (SCR55 – see “System
Control Register – FPGA/AVR” on page 30). As inputs, Port E pins that are externally pulled
Low will source current if the pull-up resistors are activated.
Port E also serves the functions of various special features. See Table 46 on page 149.
The Port E pins are input with pull-up when a reset condition becomes active, even if the clock
is not running
Input (receive) to UART(0) – See SCR52
Output (transmit) from UART(0) – See SCR52
Input (receive) to UART(1) – See SCR53
Output (transmit) from UART(1) – See SCR53
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
Operation
S ← 0
V ← 1
V ← 0
T ← 1
T ← 0
H ← 1
H ← 0
(See specific description for Sleep)
(See specific description for WDR)
For on-chip debug only
Flags
S
V
V
T
T
H
H
None
None
None
None
Rev. 1138F–FPSLI–06/02
#Clock
1
1
1
1
1
1
1
1
1
1
N/A