AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 42

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

No Clock/Oscillator
Source
Timer Oscillator
Architectural
Overview
42
AT94K Series FPSLIC
When not in use, for low static IDD, add a pull-down resistor to XTAL1.
Figure 26. No Clock/Oscillator Connections
For the timer oscillator pins, TOSC1 and TOSC2, the crystal is connected directly between the
pins. The oscillator is optimized for use with a 32.768 kHz watch crystal. An external clock sig-
nal applied to this pin goes through the same amplifier having a bandwidth of 1 MHz. The
external clock signal should therefore be in the range
0 Hz – 1 MHz.
Figure 27. Time Oscillator Connections
The AVR uses a Harvard architecture concept – with separate memories and buses for pro-
gram and data. The program memory is accessed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock-cycle. The program memory is
in-system programmable SRAM memory. With a few exceptions, AVR instructions have a sin-
gle 16-bit word format, meaning that every program memory address contains a single 16-bit
instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on
the stack. The stack is effectively allocated in the general data SRAM, as a consequence, the
stack size is only limited by the total SRAM size and the usage of the SRAM. All user pro-
grams must initialize the Stack Pointer (SP) in the reset routine (before subroutines or
interrupts are executed). The 16-bit stack pointer is read/write accessible in the I/O space.
The data SRAM can be easily accessed through the five different addressing modes sup-
ported in the AVR architecture.
A flexible interrupt module has its control registers in the I/O space with an additional global
interrupt enable bit in the status register. All the different interrupts have a separate interrupt
vector in the interrupt vector table at the beginning of the program memory. The different inter-
rupts have priority in accordance with their interrupt vector position. The lower the interrupt
vector address, the higher the priority.
The memory spaces in the AVR architecture are all linear and regular memory maps.
C
C
R
1
2
PD
NC
R
XTAL2
XTAL1
GND
B
R
S
TOSC2
TOSC1
R
PD
= 4.7 KΩ
C
C
R
R
1
2
B
S
= 33 pF
= 27 pF
= 10M
= 200K
Rev. 1138F–FPSLI–06/02