AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 44

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

X-register,
Y-register and
Z-register
ALU – Arithmetic
Logic Unit
Multiplier Unit
SRAM Data
Memory
Program and Data
Addressing Modes
44
AT94K Series FPSLIC
Registers R26..R31 have some added functions to their general-purpose usage. These regis-
ters are address pointers for indirect addressing of the SRAM. The three indirect address
registers X, Y and Z have functions as fixed displacement, automatic increment and decre-
ment (see the descriptions for the different instructions).
The high-performance AVR ALU operates in direct connection with all the 32 general-purpose
working registers. Within a single clock cycle, ALU operations between registers in the register
file are executed. The ALU operations are divided into three main categories – arithmetic, log-
ical and bit-functions.
The high-performance AVR Multiplier operates in direct connection with all the 32 general-pur-
pose working registers. This unit performs 8 x 8 multipliers every two clock cycles. See
multiplier details on page 106.
External data SRAM (or program) cannot be used with the FPSLIC AT94K family.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the register
file, registers R26 to R31 feature the indirect addressing pointer registers.
The Indirect with Displacement mode features a 63 address locations reach from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic Pre-decrement and Post-incre-
ment, the address registers X, Y and Z are decremented and incremented.
The entire data address space including the 32 general-purpose working registers and the 64
I/O registers are all accessible through all these addressing modes. See the next section for a
detailed description of the different addressing modes.
The embedded AVR core supports powerful and efficient addressing modes for access to the
program memory (SRAM) and data memory (SRAM, Register File and I/O Memory). This sec-
tion describes the different addressing modes supported by the AVR architecture.
Register Direct, Single-register Rd
The operand is contained in register d (Rd).
Register Direct, Two Registers Rd and Rr
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).
I/O Direct
Operand address is contained in 6 bits of the instruction word. n is the destination or source
register address.
Data Direct
A 16-bit data address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the
destination or source register.
Data Indirect with Displacement
Operand address is the result of the Y- or Z-register contents added to the address contained
in 6 bits of the instruction word.
Rev. 1138F–FPSLI–06/02