AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 48

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

AT94K Register Summary (Continued)
Note:
The embedded AVR core I/Os and peripherals, and all the virtual FPGA peripherals are placed in the I/O space. The differ-
ent I/O locations are directly accessed by the IN and OUT instructions transferring data between the 32 x 8 general-
purpose working registers and the I/O space. I/O registers within the address range $00 – $1F are directly bit-accessible
using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC
instructions. When using the I/O specific instructions IN, OUT, the I/O register address $00 – $3F are used, see Figure 32.
When addressing I/O registers as SRAM, $20 must be added to this address. All I/O register addresses throughout this
document are shown with the SRAM address in parentheses.
48
$0D ($2D)
$0C ($2C)
$0E ($2E)
$0B ($2B)
$0A ($2A)
$16 ($36)
$15 ($35)
$14 ($34)
$13 ($33)
$12 ($32)
$11 ($31)
$10 ($30)
$0F ($2F)
$09 ($29)
$08 ($28)
$07 ($27)
$06 ($26)
$05 ($25)
$04 ($24)
$03 ($23)
$02 ($22)
$01 ($21)
$00 ($20)
Address
1. The On-chip Debug Register (OCDR) is detailed on the “FPSLIC On-chip Debug System” distributed within Atmel and select
AT94K Series FPSLIC
third-party vendors only under Non-Disclosure Agreement (NDA). Contact [e-mail] for a copy of this document.
Name
FISUC
FISUB
FISUA
FISCR
PORTD
DDRD
PIND
Reserved
Reserved
Reserved
UDR0
UCSR0A
UCSR0B
UBRR0
OCDR
(Reserved)
PORTE
DDRE
PINE
Reserved
UDR1
UCSR1A
UCSR1B
UBRR1
FPGA I/O Select, Interrupt Mask/Flag Register C (Reserved on AT94K05)
FPGA I/O Select, Interrupt Mask/Flag Register B
FPGA I/O Select, Interrupt Mask/Flag Register A
UART0 I/O Data Register
UART0 Baud-rate Register
UART1 I/O Data Register
UART1 Baud-rate Register
PORTD7
PORTE7
RXCIE0
RXCIE1
DDRD7
DDRE7
FIADR
PIND7
PINE7
RXC0
RXC1
IDRD
Bit 7
PORTD6
PORTE6
DDRD6
TXCIE0
TXCIE1
DDRE6
PIND6
PINE6
TXC0
TXC1
Bit 6
PORTD5
PORTE5
UDRIE0
UDRIE1
DDRD5
UDRE0
DDRE5
UDRE1
PIND5
PINE5
Bit 5
PORTD4
PORTE4
DDRD4
RXEN0
DDRE4
RXEN1
PIND4
PINE4
Bit 4
FE0
FE1
PORTD3
PORTE3
DDRD3
DDRE3
TXEN0
TXEN1
PIND3
PINE3
Bit 3
OR0
OR1
PORTD2
PORTE2
DDRD2
CHR90
DDRE2
CHR91
PIND2
PINE2
Bit 2
PORTD1
PORTE1
DDRD1
DDRE1
RXB80
RXB81
PIND1
PINE1
XFIS1
U2X0
U2X1
Bit 1
PORTD0
PORTE0
MPCM0
MPCM1
DDRD0
DDRE0
TXB80
TXB81
XFIS0
PIND0
PINE0
Bit 0
Rev. 1138F–FPSLI–06/02
Reserved
Reference
54, 56
54, 56
54, 56
Page
124
124
124
101
101
103
105
126
126
126
101
101
103
105
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