AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 50

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

50
AT94K Series FPSLIC
Status Register – SREG
The AVR status register
Note:
• Bit 7 - I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individ-
ual interrupt enable control is then performed in separate control registers. If the global
interrupt enable register is cleared (zero), none of the interrupts are enabled independent of
the individual interrupt enable settings. The I-bit is cleared by the hardware after an interrupt
has occurred, and is set by the RETI instruction to enable subsequent interrupts.
• Bit 6 - T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and des-
tination for the operated bit. A bit from a register in the register file can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the register file by the
BLD instruction.
• Bit 5 - H: Half-carry Flag
The half-carry flag H indicates a half-carry in some arithmetic operations.
• Bit 4 - S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the negative flag N and the two’s complement
overflow flag V.
• Bit 3 - V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics.
• Bit 2 - N: Negative Flag
The negative flag N indicates a negative result from an arithmetical or logical operation.
• Bit 1 - Z: Zero Flag
The zero flag Z indicates a zero result from an arithmetical or logical operation.
• Bit 0 - C: Carry Flag
The carry flag C indicates a carry in an arithmetical or logical operation.
Stack Pointer – SP
The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O
space locations $3E ($5E) and $3D ($5D). Future versions of FPSLIC may support up to 64K
Bytes of memory; therefore, all 16 bits are used.
Bit
$3F ($5F)
Read/Write
Initial Value
Bit
$3E ($5E)
$3D ($5D)
Read/Write
Initial Value
1. Note that the status register is not automatically stored when entering an interrupt routine
and restored when returning from an interrupt routine. This must be handled by software.
7
I
R/W
0
15
SP15
SP7
7
R/W
R/W
0
0
(1)
6
T
R/W
0
14
SP14
SP6
6
R/W
R/W
0
0
– SREG – at I/O space location $3F ($5F) is defined as:
5
H
R/W
0
13
SP13
SP5
5
R/W
R/W
0
0
4
S
R/W
0
12
SP12
SP4
4
R/W
R/W
0
0
3
V
R/W
0
11
SP11
SP3
3
R/W
R/W
0
0
2
N
R/W
0
10
SP10
SP2
2
R/W
R/W
0
0
1
Z
R/W
0
9
SP9
SP1
1
R/W
R/W
0
0
Rev. 1138F–FPSLI–06/02
0
C
R/W
0
8
SP8
SP0
0
R/W
R/W
0
0
SREG
SPH
SPL