AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 56

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

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AT94K Series FPSLIC
Figure 33. Out Instruction – AVR Writing to the FPGA
Note:
Figure 34. In Instruction – AVR Reading FPGA
Notes:
(FPGA DATA OUT)
(FISUA, B, C or D)
(FISUA, B, C or D)
SYSTEM CLOCK)
FPGA CLOCK
(FPGA DATA IN)
AVR CLOCK
AVR CLOCK
FPGA IOWE
AVR IOADR
FPGA IORE
SELECT "n"
AVR IOADR
SELECT "n"
AVR DBUS
AVR DBUS
1. AVR expects Write to be captured by the FPGA upon posedge of the AVR clock.
1. AVR captures read data upon posedge of the AVR clock.
2. At the end of an FPGA read cycle, there is a chance for the AVR data bus contention
AVR IOWE
(SET TO AVR
AVR IORE
AVR INST
AVR INST
FPGA I/O
FPGA I/O
between the FPGA and another peripheral to start to drive (active IORE at new address ver-
sus FPGAIORE + Select “n”), but since the AVR clock would have already captured the data
from AVR DBUS (= FPGA Data Out), this is a “don’t care” situation.
OUT INSTRUCTION
IN INSTRUCTION
WRITE DATA VALID
READ DATA VALID
(1)
(2)
(2)
Rev. 1138F–FPSLI–06/02
(1)