AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 65

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

Rev. 1138F–FPSLI–06/02
• Bit 2 - OCIE2: Timer/Counter2 Output Compare Interrupt Enable
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed
if a Compare match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in the
Timer/Counter interrupt flag register – TIFR.
• Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Inter-
rupt Flag Register – TIFR.
• Bit 0 - OCIE0: Timer/Counter0 Output Compare Interrupt Enable
When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed
if a Compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
Timer/Counter Interrupt Flag Register – TIFR
• Bit 7 - TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by the
hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is
cleared by writing a logic 1 to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1
Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is
executed. In PWM mode, this bit is set when Timer/Counter1 advances from $0000.
• Bit 6 - OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the
data in OCR1A – Output Compare Register 1A. OCF1A is cleared by the hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a
logic 1 to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare Interrupt
Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is
executed.
• Bit 5 - OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the
data in OCR1B – Output Compare Register 1B. OCF1B is cleared by the hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF1B is cleared by writing a
logic 1 to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match
Interrupt Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Inter-
rupt is executed.
• Bit 4 - TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by the
hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is
cleared by writing a logic 1 to the flag. When the I-bit in SREG, and TOIE2 (Timer/Counter1
Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow Interrupt is
executed. In PWM mode, this bit is set when Timer/Counter2 advances from $00.
Bit
$38 ($58)
Read/Write
Initial Value
7
TOV1
R/W
0
6
OCF1A
R/W
0
5
OCF1B
R/W
0
4
TOV2
R/W
0
3
ICF1
R/W
0
AT94K Series FPSLIC
2
OCF2
R/W
0
1
TOV0
R/W
0
0
OCF0
R/W
0
TIFR
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