AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 86

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AT94K05AL

Manufacturer Part Number
AT94K05AL
Description
Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
Manufacturer
ATMEL Corporation
Datasheet

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8-bit
Timers/Counters
T/C0 and T/C2
86
AT94K Series FPSLIC
Figure 49. Timer/Counter2 Prescaler
Special Function I/O Register – SFIOR
• Bits 7..2 - Res: Reserved Bits
These bits are reserved bits in the FPSLIC and are always read as zero.
• Bit 1 - PSR2: Prescaler Reset Timer/Counter2
When this bit is set (one) the Timer/Counter2 prescaler will be reset. The bit will be cleared by
the hardware after the operation is performed. Writing a zero to this bit will have no effect. This
bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit
is written when Timer/Counter2 is operating in asynchronous mode; however, the bit will
remain as one until the prescaler has been reset. See “Asynchronous Operation of
Timer/Counter2” on page 94 for a detailed description of asynchronous operation.
• Bit 0 - PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is set (one) the Timer/Counter1 and Timer/Counter0 prescaler will be reset. The
bit will be cleared by the hardware after the operation is performed. Writing a zero to this bit
will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler
and a reset of this prescaler will affect both timers. This bit will always be read as zero.
Figure 50 shows the block diagram for Timer/Counter0. Figure 51 shows the block diagram for
Timer/Counter2.
Bit
$30 ($50)
Read/Write
Initial Value
TOSC1
PSR2
CS20
CS21
CS22
AS2
CK
7
-
R
0
6
-
R
0
PCK2
5
-
R
0
Clear
4
-
R
0
TIMER/COUNTER2 CLOCK SOURCE
0
3
-
R
0
10-BIT T/C PRESCALER
TCK2
2
-
R
0
1
PSR2
R/W
0
0
PSR10
R/W
0
Rev. 1138F–FPSLI–06/02
SFIOR

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