AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 96

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AT94K05AL

Manufacturer Part Number
AT94K05AL
Description
Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
Manufacturer
ATMEL Corporation
Datasheet

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The 16-bit Timer/Counter1 can select the clock source from CK, prescaled CK, or an external
pin. In addition it can be stopped as described in section “Timer/Counter1 Control Register B –
TCCR1B” on page 98. The different status flags (overflow, compare match and capture event)
are found in the Timer/Counter Interrupt Flag Register – TIFR. Control signals are found in the
Timer/Counter1 Control Registers – TCCR1A and TCCR1B. The interrupt enable/disable set-
tings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register – TIMSK.
When Timer/Counter1 is externally clocked, the external signal is synchronized with the oscil-
lator frequency of the CPU. To assure proper sampling of the external clock, the minimum
time between two external clock transitions must be at least one internal CPU clock period.
The external clock signal is sampled on the rising edge of the internal CPU clock.
The 16-bit Timer/Counter1 features both a high-resolution and a high-accuracy usage with the
lower prescaling opportunities. Similarly, the high-prescaling opportunities makes the
Timer/Counter1 useful for lower speed functions or exact-timing functions with infrequent
actions.
The Timer/Counter1 supports two Output Compare functions using the Output Compare Reg-
ister 1 A and B – OCR1A and OCR1B as the data sources to be compared to the
Timer/Counter1 contents. The Output Compare functions include optional clearing of the
counter on compareA match, and actions on the Output Compare pins on both compare
matches.
Timer/Counter1 can also be used as a 8-, 9- or 10-bit Pulse Width Modulator. In this mode, the
counter and the OCR1A/OCR1B registers serve as a dual-glitch-free stand-alone PWM with
centered pulses. Alternatively, the Timer/Counter1 can be configured to operate at twice the
speed in PWM mode, but without centered pulses. Refer to page 101 for a detailed description
on this function.
The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1 con-
tents to the Input Capture Register – ICR1, triggered by an external event on the Input
Capture Pin – PE7(ICP). The actual capture event settings are defined by the Timer/Counter1
Control Register – TCCR1B.
Figure 55. ICP Pin Schematic Diagram
ICPE
ICPE: Input Capture Pin Enable
If the noise canceler function is enabled, the actual trigger condition for the capture event is
monitored over four samples, and all four must be equal to activate the capture flag.
AT94K Series FPSLIC
96
Rev. 1138F–FPSLI–06/02

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