ADS824 Burr-Brown Corporation, ADS824 Datasheet - Page 11

• Manufacturer Part Number: ADS824
• Description: 10-Bit/ 70MHz Sampling ANALOG-TO-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

the resistive reference ladder. The bandgap reference circuit
includes logic functions that allows setting the analog input
swing of the ADS824 to either a 1Vp-p or 2Vp-p full-scale
range by simply tying the RSEL pin to a Low or High
potential, respectively. While operating the ADS824 in the
external reference mode, the buffer amplifiers for the REFT
and REFB are disconnected from the reference ladder.
As shown, the ADS824 has internal 50k
at the range select pin (RSEL) and reference select pin
(INT/EXT). Leaving these pins open configures the ADS824
for a 2Vp-p input range and external reference operation.
Setting the ADS824 up for internal reference mode requires
to bringing the INT/EXT pin low.
The reference buffers can be utilized to supply up to 1mA
(sink and source) to external circuitry. The resistor ladder of
the ADS824 is divided into several segments and has two
additional nodes, ByT and ByB, which are brought out for
external bypassing only (Figure 6). To ensure proper opera-
tion with any reference configurations, it is necessary to
provide solid bypassing at all reference pins in order to keep
the clock feedthrough to a minimum. All bypassing capaci-
tors should be located as close to their respective pins as
possible.
FIGURE 7. Alternative Circuit to Generate CM Voltage.
FIGURE 8. Configuration Example for External Reference Operation.
A - Short for 1Vp-p Input Range
B - Short for 2Vp-p Input Range (Default)
+3.5V
REFT
0.1 F
+2.5V
CMV
1.0k
V
R
DC
IN
1
REFT = REFB +0.8V to +3.75V
External Top Reference
ADS824
+2.5V
CMV
1.0k
R
2
IN
IN
pull-up resistors
REFB
+1.5V
0.1 F
REFT
+5V
+VS
INT/EXT
ByT
11
4 x 0.1µF || 2.2µF
The common-mode voltage available at the CM-pin may be
used as a bias voltage to provide the appropriate offset for
the driving circuitry. However, care must be taken not to
appreciably load this node, which is not buffered and has a
high impedance. An alternative way of generating a com-
mon-mode voltage is given in Figure 7. Here, two external
precision resistors (tolerance 1% or better) are located
between the top and bottom reference pins. The common-
mode voltage, CMV, will appear at the midpoint.
EXTERNAL REFERENCE OPERATION
For even more design flexibility, the internal reference can
be disabled and an external reference voltage be used. The
utilization of an external reference may be considered for
applications requiring higher accuracy, improved tempera-
ture performance, or a wide adjustment range of the
converter’s full-scale range. Especially in multichannel
applications, the use of a common external reference has the
benefit of obtaining better matching of the full-scale range
between converters.
The external references can vary as long as the value of the
external top reference REFT
(V
reference REFB
See Figure 8.
DIGITAL INPUTS AND OUTPUTS
Clock Input Requirements
Clock jitter is critical to the SNR performance of high speed,
high resolution A/D converters. Clock jitter leads to aperture
jitter (t
ADS824 samples the input signal on the rising edge of the
CLK input. Therefore, this edge should have the lowest
possible jitter. The jitter noise contribution to total SNR is
ADS824
GND
S
– 1.25V) and (REFB + 0.8V), and the external bottom
B
RSEL
A
), which adds noise to the signal being converted. The
A
ByB
EXT
REFB
GND
stays within 1.25V and (REFT – 0.8V).
REFB = REFT –0.8V to +1.25V
External Bottom Reference
EXT
ADS824
stays within the range of
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