AD1821 Analog Devices, AD1821 Datasheet - Page 17

• Manufacturer Part Number: AD1821
• Manufacturer: Analog Devices

At start-up (after pin reset), there are exactly 12 time slots per frame. The frame rate will be 57,291 and 2/3 Hz (11 MHz sclk/
(16 bits
frame mode, where the first 12 and second 12 slots in the ADSP-21xx frame are identical.
The frame rate can be changed from its default by a write to the DFS(2:0) bits in register 33. Rate choices are: Maximum (57,291
and 2/3 Hz default), SS capture rate, SS playback rate, FM rate, I
than 57,261 and 2/3 Hz, extra SCLK periods are added to fill up the time. The number of SCLK periods added will vary somewhat
from frame to frame.
To control the sample data flow of each channel through the DSP Port, valid input, valid output and request bits are located in the
control and status words. If the specified channel sample rate is equal to the frame rate, these bits may be ignored since they will
always be set to “1”.
By default, the DSP serial port allows only codec sample data I/O to be monitored. Intercept modes must be enabled to make substi-
tutions in sample data flow to and from the codec. There are five bits in SS register 33, which enable intercept mode for SS capture,
SS playback, FM playback, I
Control Word Input (Slot 0 SDI)
IA [5:0]
R/W
ALIVE
IS0VI
IS1VI
FMVI
REV. 0
ALIVE
FCLR
12 slots)). Interfacing with an Analog Devices 21xx family DSP can be achieved by putting the ADSP-21xx in 24 slot per
15
7
Time Slot
0
1
2
3
4
5
6
7
8
9
10
11
*This data is ignored by the AD1821 unless the channel pair is in intercept mode (see below).
SS = Sound System Mode
SB = SoundBlaster Mode
Read/Write request. Either a read from or a write to an SS indirect register occurs every frame. Setting this bit ini-
DSP port alive bit. When set, this bit indicates to the power-down timer that the DSP port is active. When cleared,
FM Synthesis Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for the
Indirect Register Address. Sound System Indirect Register Address defines the address of indirect registers shown
in Table VI.
tiates an SS indirect register read while clearing this bit initiates an SS indirect register write.
this bit indicates that the DSP port is inactive.
I
port 0 channel pair, or (2) The AD1821 did not request data from the I
frame. Otherwise, setting this bit indicates that slots 10 and 11 contain valid right and left I
data. When this bit is cleared, data in slots 10 and 11 is ignored.
I
1 channel pair or (2) The AD1821 did not request data from the I
erwise, setting this bit indicates that Slots 8 and 9 contain valid right and left I
this bit is cleared, data in slots 8 and 9 is ignored.
FM synthesis channel pair or (2) The AD1821 did not request data from the FM synthesis channel pair in the pre-
vious frame (see the FMRQ Bit 9 in the status word output). Otherwise, setting this bit to 1 indicates that slots 6
and 7 contain valid right and left FM synthesis channel substitution data. When this bit is reset to 0, data in slots 6
and 7 is ignored.
2
2
S Port 0 Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for the I
S Port 1 Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for I
RES
R/W
14
6
SDI Pin
Control Word Input
Control Register Data Input
* SS/SB ADC Right Input (to ISA)
* SS/SB ADC Left Input (to ISA)
* SS/SB DAC Right Input (to Codec)
* SS/SB DAC Left Input (to Codec)
* FM DAC Right Input (to Codec)
* FM DAC Left Input (to Codec)
* I
* I
* I
* I
2
S Port (1) playback and I
2
2
2
2
S (1) DAC Right Input (to Codec)
S (1) DAC Left Input (to Codec)
S (0) DAC Right Input (to Codec)
S (0) DAC Left Input (to Codec)
RES
13
5
Table I. DSP Port Time Slot Map
2
SSCVI
S Port (0) playback.
12
4
–17–
2
S Port (1) rate, or I
SDO Pin
Status Word Output
Control Register Data Output
SS/SB DAC Right Output (from ISA)
SS/SB DAC Left Output (from ISA)
I
I
I
I
SS/SB ADC Right Output (from Codec)
SS/SB ADC Left Output (from Codec)
FM DAC Right Output (from FM Synth Block)
FM DAC Left Output (from FM Synth Block)
IA[5:0]
2
2
2
2
SSPVI
S (1) DAC Right Output (from I
S (1) DAC Left Output (from I
S (0) DAC Right Output (from I
S (0) DAC Left Output (from I
11
3
2
S port channel pair in the previous frame. Oth-
2
S Port (0) rate. When the frame rate is less
FMVI
10
2
2
S port 0 channel pair in the previous
2
S Port 1 substitution data. When
IS1VI
2
2
S Port [1])
S Port [0])
2
2
1
9
S Port [1])
S Port [0])
2
S Port 0 substitution
AD1821
IS0VI
8
0
2
S port
2
S