AD1821 Analog Devices, AD1821 Datasheet - Page 23

• Manufacturer Part Number: AD1821
• Manufacturer: Analog Devices

[Base+0]
INADR [5:0] (RW) Indirect Address for Sound System (SS). These bits are used to access the Indirect Registers shown in Table VIII.
VBL
CRDY
[Base+1]
SI
GI
RI
DI
VI
TI
CI
PI
[Base+2]
[Base+3]
Indirect SS
Data [15:0]
REV. 0
CRDY
Chip/Modem Status/Indirect Address
Interrupt Status
(RO) SoundBlaster generated Interrupt.
(RW) Game Interrupt (Sticky, Write “0” to Clear).
(RW) Ring Interrupt (Sticky, Write “0” to Clear).
(RW) DSP Interrupt (Sticky, Write “0” to Clear).
(RW) Volume Interrupt (Sticky, Write “0” to Clear).
(RW) Capture Interrupt. This bit indicates that there is an interrupt pending from the capture DMA count register.
(RW) Playback Interrupt. This bit indicates that there is an interrupt pending from the playback DMA count
Indirect SS Data Low Byte
Indirect SS Data High Byte
(RW) Timer Interrupt. This bit indicates there is an interrupt pending from the timer count registers. (Sticky,
Indirect Sound System Data. Data in this register is written to the Sound System Indirect Register specified by the
address contained in INDAR [5:0], Sound System Direct Register [Base+0]. Data is written when the Indirect SS
Data High Byte value is loaded.
7
7
(RO) AD1821 Ready. The AD1821 asserts this bit when AD1821 can accept data.
7
PI
7
All registers data must be written in pairs, low byte followed by high byte, by loading the Indirect SS Data
Registers, (Base+2) and (Base+3).
Volume Button Location. When using an EEPROM to configure the PnP state of the AD1821, this bit determines
whether PQFP Pins 1 and 2 (TQFP Pins 99 and 100) are used for VOL_UP and VOL_DN or I2S0_DATA and
I2S0_LRCLK respectively.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Write “0” to Clear).
0
1
(Sticky, Write “0” to Clear).
0
1
register. (Sticky, Write “0” to Clear).
0
1
6
6
VBL
No interrupt
SoundBlaster interrupt pending
No interrupt
An interrupt is pending due to Digital Game Port data ready
No interrupt
An interrupt is pending due to a Hardware Ring pin being asserted
No interrupt
An interrupt is pending due to a write to the DIT bit in indirect register [33] bit <13>
No interrupt
An interrupt is pending due to Hardware Volume Button being pressed
No interrupt
Interrupt is pending from the timer count register
No interrupt
Interrupt is pending from the capture DMA count register
No interrupt
Interrupt is pending from the playback DMA count register
CI
6
6
I2S0_DATA and I2S0_LRCLK
VOL_UP and VOL_DN
AD1821 not ready
AD1821 ready
5
5
TI
5
Indirect SS Data [15:8]
5
Indirect SS Data [7:0]
4
4
VI
4
4
INADR[5:0]
3
3
DI
3
3
–23–
2
2
2
RI
2
1
1
1
GI
1
0
0
0
SI
0
RESET = [0x00]
RESET = [0xXX]
RESET = [0xXX]
RESET = [0x00]
AD1821