AD1821 Analog Devices, AD1821 Datasheet - Page 24

• Manufacturer Part Number: AD1821
• Manufacturer: Analog Devices

AD1821
[Base+4] PIO Debug
All bits in this register are sticky until any write that clears all bits to 0.
ORL/ORR (RO)
[1:0]
COR
PUR
[Base+5]
CUL
CLR
CDR
CFH
PUL
PLR
PDR
PFH
(RO)
(RO)
PIO Status
(RO)
(RO)
(RO)
(RO)
(RO)
(RO)
(RO)
(RO)
7
PFH
7
RES
Overrange Left/Right detect. These bits record the largest output magnitude on the ADC right and left
Capture Upper/Lower Sample. This bit indicates whether the PIO capture data ready is for the upper
Capture FIFO Half Full. (FIFO has at least 32 bytes before full.)
Playback Upper/Lower Sample. This bit indicates whether the PIO playback data needed is for the upper or
Playback Left/Right Sample. This bit indicates whether the PIO playback data needed is or the left channel
channels and are cleared to 00 after any write to this register. The peak amplitude as recorded by these bits is
“sticky,” i.e., the largest output magnitude recorded by these bits will persist until these bits are explicitly
cleared. They are also cleared by powering down the chip.
Capture Over Run. The codec sets (1) this bit when capture data is not read within one sample period after the
capture FIFO fills. When COR is set, the FIFO is full and the codec discards any new data generated. The
codec clears this bit immediately after a 4 byte capture sample is read.
Playback Under Run. The codec sets (1) this bit when playback data is not written within one sample period af-
ter the playback FIFO empties. The codec clears (0) this bit immediately after a 4 byte playback sample is writ-
ten. When PUR is set, the playback channel has “run out” of data and either plays back a mid-scale value or
repeats the last sample.
or lower byte of the channel.
0
1
Capture Left/Right Sample. This bit indicates whether the PIO capture data waiting is for the left channel ADC
or the right channel ADC.
0
1
Capture Data Ready. The PIO Capture Data register contains data ready for reading by the host. This bit should be
used only when direct programmed I/O data transfers are desired (FIFO has at least 4 bytes before full).
0
1
lower byte of the channel.
0
1
DAC or the right channel DAC.
0
1
Playback Data Ready. The PIO Playback data register is ready for more data. This bit should only be used
when direct programmed I/O data transfers are desired (FIFO can take at least 4 bytes).
0
1
Playback FIFO Half Empty. FIFO can take at least 32-bytes, 8 groups of 4-bytes.
6
PDR
Lower byte ready
Upper byte ready or any 8-bit mode
Right channel
Left channel or mono
ADC is stale. Do not reread the information
ADC data is fresh. Ready for next host data read
Lower byte needed
Upper byte needed or any 8-bit mode
Right channel needed
Left channel or mono
DAC data is still valid. Do not overwrite
DAC data is stale. Ready for next host data write value
6
PUR
5
PLR
ORL/ORR Over/Under Range Detection
00
01
10
11
5
COR
4
PUL
4
Less than –1 dB Underrange
Between –1 dB and 0 dB Underrange
Between 0 dB and 1 dB Overrange
Greater than 1 dB Overrange
3
CFH
ORR[1:0]
3
–24–
2
CDR
2
1
CLR
ORL[1:0]
1
0
CUL
0
RESET = [0x00]
RESET = [0x00]
REV. 0