AD1821 Analog Devices, AD1821 Datasheet - Page 34

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AD1821

Manufacturer Part Number
AD1821
Description
Manufacturer
Analog Devices
Datasheet

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AD1821
LAGC
MCM
PIA [3:0]
PIM
MCA [4:0]
M20
MCM
RAG [3:0]
RAGC
LAG [3:0]
LAGC
RAS [2:0]
000
001
010
011
100
101
110
111
I
I
COF [3:0]
CNP
CDE
WSE
WSE
[32] CHIP CONFIGURATION
2
2
[19] MIC/PHONE_IN GAIN/ATTENUATION
[20] ADC SOURCE SELECT AND ADC PGA
SF0 [1:0]
SF1 [1:0]
7
7
7
CDE
M20
6
6
6
LAS [2:0]
RES
PHONE_IN Attenuation. The LSB represents –3 dB, 0000 = 0 dB and the range is 0 dB to –45 dB.
PHONE_IN Mute.
Microphone Attenuation. The LSB represents –1.5 dB, 00000 = +12 dB and the range is 12 dB to –34.5 dB.
Microphone 20 dB Gain. The M20-bit enables the Microphone +20 dB gain stage.
Microphone Mute.
Right ADC Gain Control ADC source select and Gain. For Gain, LSB represents +1.5 dB, 0000 = 0 dB
and the range is 0 dB to +22.5 dB.
Right Automatic Gain Control (AGC) Enable, 0 = Enabled, 1 = Disabled.
Left ADC Gain Control ADC source select and Gain. For Gain, LSB represents +1.5 dB, 0000 = 0 dB
and the range is 0 dB to +22.5 dB.
Left Automatic Gain Control (AGC) Enable, 0 = Enabled, 1 = Disabled.
ADC Right Input Source
R_LINE
R_OUT
R_CD
R_SYNTH
R_VID
Mono Mix
Reserved
Reserved
I
Clock Output Frequency. Programmable clock output on PCLKO pin is determined using the following formula
PCLKO = 256
SS [38]. If COF > 11, then PCLKO is disabled.
Capture not equal to Playback.
0 = Capture equals Playback. The capture sample rate is determined by the playback sample rate in SS [02].
1 = Capture not equal to Playback.
CD Enable, Set to “1” when a CD player is connected to I
Sound System Enable.
0 = SoundBlaster Mode.
1 = Sound System Mode under Windows.
Note: When in SoundBlaster Mode, the Codec ADC and DAC channels will be used solely for converting
SoundBlaster data.
2
RES
S Port Configuration for serial data type.
5
5
5
CNP
4
4
4
00
01
10
11
PCR/2
3
3
3
Disabled
Right Justified
I
Left Justified
2
RES
S Justified
MCA [4:0]
COF
LAG [3:0]
2
2
2
where COF = 0:11 and PCR is the value of the Programmable Clock Rate Register,
IME
1
1
1
IMR
0
0
0
–34–
RAGC
PIM
7
7
7
LAS [2:0]
000
001
010
011
100
101
110
111
COF [3:0]
6
2
6
6
S (0).
RES
RAS [2:0]
5
5
5
ADC Left Input Source
L_LINE
L_OUT
L_CD
L_SYNTH
L_VID
MIC
PHONE_IN
Reserved
4
4
4
I
3
PIA [3:0]
3
3
2
SF1 [1:0]
DEFAULT = [0x00F0]
DEFAULT = [0x8888]
DEFAULT = [0x0000]
RAG [3:0]
2
2
2
I
1
1
1
2
SF0 [1:0]
RES
REV. 0
0
0
0

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