STK15C88 Simtek, STK15C88 Datasheet - Page 5
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STK15C88
Manufacturer Part Number
STK15C88
Description
32Kx8 PowerStore nvSRAM
Manufacturer
Simtek
Datasheet
1.STK15C88.pdf
(14 pages)
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Document Control #ML0016 Rev 0.3
SRAM WRITE CYCLES #1 & #2
Note i:
Note j:
SRAM WRITE CYCLE #1: W Controlled
SRAM WRITE CYCLE #2: E Controlled
NO.
12
13
14
15
16
17
18
19
20
21
ADDRESS
DATA OUT
ADDRESS
DATA OUT
DATA IN
February, 2007
DATA IN
t
WLQZ
t
t
t
t
t
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be ≥ V
t
t
t
t
WLWH
DVWH
WHDX
WHQX
ELWH
AVWH
WHAX
AVWL
AVAV
#1
W
E
W
E
h, i
SYMBOLS
t
t
t
t
t
t
t
t
WLEH
ELEH
DVEH
EHDX
AVEH
EHAX
AVAV
AVEL
#2
IH
t
AVWL
18
during address transitions.
t
AVEL
18
t
t
t
t
t
t
t
t
Alt.
t
t
WC
WP
CW
DW
WR
OW
DH
AW
WZ
AS
PREVIOUS DATA
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
t
WLQZ
t
20
AVEH
17
t
AVWH
17
t
WLWH
13
t
ELWH
j
14
PARAMETER
t
AVAV
j
12
t
AVAV
12
5
HIGH IMPEDANCE
t
ELEH
14
t
WLEH
13
HIGH IMPEDANCE
t
DVWH
15
t
DVEH
15
DATA VALID
DATA VALID
t
WHDX
t
STK15C88-25
WHAX
16
MIN
19
t
25
20
20
10
20
t
EHDX
0
0
0
5
EHAX
16
19
(V
t
WHQX
21
MAX
CC
10
= 5.0V
STK15C88-45
MIN
45
30
30
15
30
0
0
0
5
STK15C88
MAX
15
±
10%)
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns