STK672-080 Sanyo Semicon Device, STK672-080 Datasheet - Page 8

• Manufacturer Part Number: STK672-080
• Description: Stepping Motor Driver (Sine Wave Drive) Output Current : 2.8 A (No Heat Sink)
• Manufacturer: Sanyo Semicon Device

Input Signal Functions and Timing
• CLK (phase switching clock)
• CWB (Method for setting the rotation direction)
• ENABLE (Controls the on/off state of the A, A, B, and B excitation drive outputs and selects either operating or hold
Pin circuit type: Built-in pull-up resistor (20 kΩ, typical) CMOS Schmitt trigger structure
Function
Input frequency range: DC to 50 kHz
Minimum pulse width: 10 µs
Duty: 40 to 60% (However, the minimum pulse width takes precedence when M3 is high.)
Pin circuit type: Built-in pull-up resistor (20 kΩ, typical) CMOS Schmitt trigger structure
Built-in multi-stage noise rejection circuit
Function
—When M3 is high or open: The phase excited (driven) is advanced one step on each CLK rising edge.
—When M3 is low: The phase is advanced one step by both rising and falling edges, for a total of two steps per cycle.
Pin circuit type: Built-in pull-up resistor (20 kΩ, typical) CMOS Schmitt trigger structure
Function
—When CWB is low: The motor turns in the clockwise direction.
—When CWB is high: The motor turns in the counterclockwise direction.
Notes: When M3 is low, the CWB input must not be changed for about 6.25 µs before or after a rising or falling edge
as the internal state of this hybrid IC.)
—When ENABLE is high or open: Normal operating state
—When ENABLE is low: This hybrid IC goes to the hold state and excitation drive output (motor current) is forcibly
Phase excitation counter clock
on the CLK input.
Control output timing
System clock
CLK input
turned off. In this mode, the hybrid IC system clock is stopped and no inputs other than the
reset input have any effect on the hybrid IC state.
CLK Input Acquisition Timing (M3 = Low)
Control output switching timing
STK672-080
Excitation counter up/down
A13264
No. 6507-8/17