Q2686 Wavecom, Q2686 Datasheet - Page 37

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Q2686

Manufacturer Part Number
Q2686
Description
Wireless CPU
Manufacturer
Wavecom
Datasheet

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The rise and fall time of the reception signals (mainly CT103) must be less than
300 ns.
The maximum baud rate of UART1 is 115 Kbit/s for the firmware 6.60 and 921
Kbit/s for the later firmware versions.
Recommendation:
The Q2686 Wireless CPU
signals. In particular, it is recommended to use RTS and CTS for hardware flow
control in order to avoid data corruption during transmission.
For use with 5-wire serial interface
For use with 4-wire serial interface
For use with 2-wire serial interface
This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without
prior written agreement.
WM_PRJ_Q2686_PTS_001-007
(and forbidden for AT command or modem use)
configure the AT command (AT+IFC=0,0 see AT commands interface
Guide [7]).
[7] for more information.
Signal: CT103/TXD1*, CT104/RXD1*, ~CT105/RTS1*, ~CT106/CTS1*
The signal ~CT108-2/DTR1* must be managed by following the V24
protocol signalling, if you want to use the slow idle mode.
Other signals and their multiplexes are not available.
Please refer to technical appendixes of AT commands interface Guide [7]
for more information.
CT103/TXD1*, CT104/RXD1*, ~CT105/RTS1*, ~CT106/CTS1*
The signal ~CT108-2/DTR1* must be configured at low level.
Other signals and their multiplexes are not available.
Please refer to technical appendixes in the AT commands interface Guide
[7] for more information.
This case is possible for connected external chip, but not recommended
The external chip must be a flow control.
CT103/TXD1*, CT104/RXD1*
The signal ~CT108-2/DTR1* must be configured at low level.
The signals ~CT105/RTS1*, ~CT106/CTS1* are not used, please
The signal ~CT105/RTS1* must be configured at low level.
Other signals and their multiplexes are not available.
Please refer to technical appendixes in the AT commands interface Guide
confidential ©
®
is designed to operate using all the serial interface
Q2686 Wireless CPU
Interfaces
March 6, 2007
Page: 36 / 87
®

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