LPC47M112 SMSC Corporation, LPC47M112 Datasheet - Page 168

• Manufacturer Part Number: LPC47M112
• Description: ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with LPC Interface
Datasheet
Note 1: A logical device will be active and powered up according to the following equation:
SMSC DS – LPC47M112
Activate
Default = 0x00
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
Logical Device Control
Logical Device Control
Memory Base Address
I/O Base Address
(see Device Base I/O
Address Table)
Default = 0x00
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
Interrupt Select
Defaults :
0x70 = 0x00 or 0x06
(Note 3)
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
0x72 = 0x00,
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
DMA Channel Select
Default = 0x02 or 0x04
(Note 4)
on VCC POR, VTR POR,
HARD RESET and
SOFT RESET
32-Bit
Configuration
Logical Device
Logical
Configuration
Reserved
DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET).
The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or
clears the other.
LOGICAL DEVICE
REGISTER
Note1
Memory
Note 2
Device
Space
(0xA9-0xDF)
(0xE0-0xFE)
(0x76-0xA8)
(0x31-0x37)
(0x40-0x5F)
(0x60-0x6F)
(0x70,0x72)
(0x71,0x73)
(0x74,0x75)
(0x38-0x3f)
ADDRESS
0x60,2,... =
0x61,3,... =
addr[15:8]
addr[7:0]
(0x30)
0xFF
Bits[7:1] Reserved, set to zero.
Bit[0]
= 1
= 0
Vendor Defined - Reserved - Writes are
ignored, reads return 0.
Reserved – Writes are ignored, reads return 0.
Refer to Interrupt Configuration Register
description. Only the keyboard controller uses
Interrupt Select register 0x72. Unused register
(0x72) will ignore writes and return zero when
read.
compatible).
locations ignore writes and return zero when
read.
port.
writes and returns zero when read. Refer to
DMA Channel Configuration.
locations ignore writes and return zero when
read.
locations ignore writes and return zero when
read.
defined Logical Device Configuration
Reserved – Writes are ignored, reads return 0.
Registers 0x60 and 0x61 set the base address
for the device. If more than one base address
is required, the second base address is set by
registers 0x62 and 0x63.
Refer to Table 58 for the number of base
address registers used by each device.
Unused registers will ignore writes and return
zero when read.
0x70 is implemented for each logical device.
Reserved - not implemented. These register
Only 0x74 is implemented for FDC and Parallel
Reserved - not implemented. These register
Reserved - not implemented. These register
Reserved – Vendor Defined (see SMSC
Registers).
Reserved
Page 168
0x75 is not implemented and ignores
Interrupts default to edge high (ISA
Activates the logical device currently
selected through the Logical Device #
register.
Logical device currently selected is
inactive
DESCRIPTION
STATE
C
C
C
C
C
C
C
C
C
C
Rev. 02/02/2005