ADC12181 National Semiconductor, ADC12181 Datasheet - Page 13

• Manufacturer Part Number: ADC12181
• Description: 12-Bit/ 10 MHz Self-Calibrating/ Pipelined A/D Converter with Internal Sample & Hold
• Manufacturer: National Semiconductor

Applications Information
2.2 CAL
The level sensitive CAL input must be pulsed high for at least
three clock cycles to begin ADC calibration. For best perfor-
mance, calibration should be performed about ten seconds
after power up, after resetting the ADC, and after the tem-
perature has changed by more than 50˚C since the last
calibration was performed.
Calibration should be performed at the same clock fre-
quency that the ADC12181 will be used for conversions to
minimize offset errors. Calibration takes 4000 clock cycles.
Irrelevant data may appear during the calibration cycle.
2.3 OE Pin
The OE pin is used to control the state of the outputs. When
the OE pin is low, the output buffers go into the active state.
When the OE input is high, the output buffers are in the high
impedance state.
2.4 PD Pin
The PD pin, when high, holds the ADC12181 in a power-
down mode where power consumption is typically less than
15 mW to conserve power when the converter is not being
used. The ADC12181 will begin normal operation within t
after this pin is brought low, provided a valid CLOCK input is
present. The data in the pipeline is corrupted while in the
power down mode. The ADC12181 should be re-calibrated
after a power-down cycle to ensure optimum performance.
3.0 OUTPUTS
The ADC12181 has three analog outputs: reference output
voltages V
12 Data Output pins, Ready and OR (Out of Range).
3.1 Reference Output Voltages
The reference output voltages are made available only for
the purpose of bypassing with capacitors to a clean analog
ground. The recommended bypass capacitors are 0.1µF
ceramic chip capacitors. Do not load these pins.
3.2 Ready Output
The Ready output goes high to indicate that the converter is
ready for operation. This signal will go low when the con-
verter is in Calibration or Power Down mode.
RN
, V
RM
, and V
RP
. There are 14 digital outputs:
(Continued)
PD
13
3.3 OR (Out of Range) Output
The OR output goes high when the analog input is below
GND or above V
is in the valid range of operation (0V ≤ V
3.4 Data Outputs
The Data Outputs are TTL/CMOS compatible. The output
data format is 12 bits straight binary.
Minimizing the digital output currents will help to minimize
noise due to output switching. This can be done by connect-
ing buffers between the ADC outputs and any other circuitry.
Only one buffer input should be connected to each output.
Additionally, inserting series resistors of 47 to 56 Ohms right
at the digital outputs, close to the ADC pins, will isolate the
outputs from other circuitry and limit output currents.
4.0 POWER SUPPLY CONSIDERATIONS
Each power pin should be bypassed with a parallel combi-
nation of a 10µF capacitor and a 0.1µF ceramic chip capaci-
tor. The chip capacitors should be within 1/2 centimeter of
the power pins. Leadless chip capacitors are preferred be-
cause they provide low lead inductance.
The converter’s digital logic supply (V
lated from the supply that is used for other digital circuitry on
the board. A common power supply should be used for both
V
supply pins should be separately bypassed with a 0.1µF
ceramic capacitor and a low ESR 10µF capacitor. A ferrite
bead or inductor should be used between V
prevent noise coupling from the digital supply into the analog
circuit.
V
supplied with a potential between 2.7V and V
it easy to interface the ADC12181 with 3V or 5V logic fami-
lies. Powering the V
consumption and noise generation due to output switching.
DO NOT operate the V
V
applied simultaneously.
As is the case with all high speed converters, the ADC12181
is sensitive to power supply noise. Accordingly, the noise on
the analog supply pin should be minimized, keeping it below
100mV P-P.
A
D
A
! All power supplies connected to the device should be
(analog supply) and V
I/O is the power pin for the output driver. This pin may be
REF
D
. This output is low when the input signal
I/O from 3 Volts will also reduce power
D
D
I/O at a voltage higher than V
(digital supply), and each of these
D
) should be well iso-
IN
≤ V
D
A
. This makes
REF
www.national.com
and V
).
D
D
or
to