ADC12181 National Semiconductor, ADC12181 Datasheet - Page 7

• Manufacturer Part Number: ADC12181
• Description: 12-Bit/ 10 MHz Self-Calibrating/ Pipelined A/D Converter with Internal Sample & Hold
• Manufacturer: National Semiconductor

AC Electrical Characteristics
(Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
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Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
AGND, or V
V
, V
or V
I/O), the current at that pin should be limited
IN
IN
A
D
D
to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two.
Note 4: The absolute maximum junction temperatures (T
max) for this device is 150˚C. The maximum allowable power consumption is dictated by T
max, the
J
J
junction-to-ambient thermal resistance (θ
), and the ambient temperature, (T
), and can be calculated using the formula P
MAX = (T
max - T
)/θ
. In the 32-pin
JA
A
D
J
A
JA
TQFP, θ
is 74˚C/W, so P
MAX = 1,689 mW at 25˚C and 1,013 mW at the maximum operating ambient temperature of 75˚C. Note that the power consumption
JA
D
of this device under normal operation will typically be about 255 mW (typical power consumption + 20 mW TTL output loading). The values for maximum power
consumption listed above will be reached only when the ADC12181 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the
power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220 pf discharged through ZERO Ohms.
Note 6: See AN450, "Surface Mounting Methods and Their Effect on Product Reliability", or the section entitled "Surface Mount" found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5V above V
or to 5V below GND will not damage this device, provided current
A
is limited per Note 3. However, errors in the A/D conversion can occur if the input goes above V
or below GND by more than 100 mV. As an example, if V
is 4.75V,
A
A
the full-scale input voltage must be ≤4.85V to ensure accurate conversions.
10103908
| ≤ 100mV and separate bypassed capacitors are used at each power supply pin.
Note 8: To guarantee accuracy, it is required that |V
- V
A
D
Note 9: With the test condition for V
= +2.0V, the 12-bit LSB is 488µV.
REF
Note 10: Typical figures are at T
= T
= 25˚C, and represent most likely parametric norms.
A
J
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-scall and
zero.
Note 13: Timing specifications are tested at the TTL logic levels, V
= 0.4V for a falling edge and V
= 2.4V for a rising edge. TRI-STATE output voltage is forced
IL
IH
to 1.4V.
Note 14: Optimum SNR performance will be obtained by keeping the reference input in the 1.8V to 2.2V range. The LM4041CIM3-ADJ (SOT-23 package), the
LM4041CIZ-ADJ (TO-92 package), or the LM4041CIM-ADJ (SOT-8 package) bandgap voltage reference is recommended for this application.
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