MD5811-d256-MECH M-Systems Inc., MD5811-d256-MECH Datasheet
MD5811-d256-MECH
Related parts for MD5811-d256-MECH
MD5811-d256-MECH Summary of contents
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Mobile DiskOnChip P3 M-Systems’ x2 Technology Highlights Mobile DiskOnChip™ P3, a member of M-Systems’ DiskOnChip™ family of optimized memory solutions for new-generation mobile handsets, provides high performance and reliability using NAND flash technology. It combines Toshiba’s cutting-edge 0.13 micron NAND ...
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Performance MultiBurst read: 80 MB/sec Sustained read: 5 MB/sec Sustained write: 2.5 MB/sec Access time: Normal: 55 nsec Turbo: 33 nsec MultiBurst: 25 nsec Protection & Security-Enabling Features 16-byte Unique Identification (UID) number 6KByte user-controlled One Time Programmable (OTP) area ...
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TrueFFS Software Full hard-disk read/write emulation for transparent file system management Patented TrueFFS Flash file system management Automatic block management Data management to maximize the limit of typical flash life expectancy Dynamic virtual mapping Dynamic and static wear-leveling Programming, ...
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T C ABLE OF ONTENTS 1. Introduction ............................................................................................................................... 5 2. Product Overview ...................................................................................................................... 6 2.1 Product Description ............................................................................................................ 6 2.2 Standard Interface .............................................................................................................. 7 2.2.1 Pin/Ball Diagrams................................................................................................................. 7 2.2.2 System Interface .................................................................................................................. 9 2.2.3 Signal Description .............................................................................................................. 10 2.3 Multiplexed ...
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Turbo Operation ............................................................................................................... 31 5. Hardware Protection ............................................................................................................... 32 5.1 Method of Operation......................................................................................................... 32 5.2 Low-Level Structure of the Protected Area....................................................................... 33 6. Modes of Operation................................................................................................................. 35 6.1 Normal Mode .................................................................................................................... 36 6.2 Reset Mode ...................................................................................................................... 36 6.3 Deep ...
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DMA Control Register [1:0]............................................................................................... 52 8.16 MultiBurst Mode Control Register..................................................................................... 54 9. Booting from Mobile DiskOnChip P3..................................................................................... 55 9.1 Introduction....................................................................................................................... 55 9.2 Boot Procedure in PC-Compatible Platforms ................................................................... 55 9.3 Boot Replacement ............................................................................................................ 56 9.3.1 PC Architectures ................................................................................................................ 56 ...
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DC Electrical Characteristics Over Operating Range ........................................................ 69 11.2.4 AC Operating Conditions.................................................................................................... 70 11.3 Timing Specifications........................................................................................................ 71 11.3.1 Read Cycle Timing Standard Interface .............................................................................. 71 11.3.2 Write Cycle Timing Standard Interface .............................................................................. 73 11.3.3 Read Cycle Timing Multiplexed Interface........................................................................... ...
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I NTRODUCTION This data sheet includes the following sections: Section 1: Overview of data sheet contents Section 2: Product overview, including a brief product description, ball diagrams and signal descriptions Section 3: Theory of operation for the major building ...
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P O RODUCT VERVIEW 2.1 Product Description Mobile DiskOnChip P3, packed in the smallest available FBGA package with 256Mb (32MB) capacity single-die device with an embedded thin flash controller and flash memory. It uses Toshiba’s cutting-edge, 0.13 ...
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Standard Interface 2.2.1 Pin/Ball Diagrams See Figure 1 and Figure 2 for the Mobile DiskOnChip P3 256Mb pinout/ballout for the standard interface. To ensure proper device functionality, pins/balls marked RSRVD are reserved for future use and should not be ...
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FBGA Package A0/ G VSS DPD H CE# OE# J RSRVD ...
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System Interface See Figure 3 for a simplified I/O diagram for a standard interface of Mobile DiskOnChip P3 256Mb. CE#, OC#, WE# A[12:0] D]15:0] System Interface Figure 3: Standard Interface Simplified I/O Diagram (Mobile DiskOnChip P3 256Mb) 9 Mobile ...
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Signal Description Mobile DiskOnChip P3 TSOP-I and FBGA packages support identical signals. The related pin and ball designations are listed in the signal descriptions, presented in logic groups, in Table 1 and Table 2. TSOP-I Package Table 1: Signal ...
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Signal Pin No. DMARQ# 21 IRQ# 47 DPD 19 VCC 12 VCCQ 37 VSS 13, 25, 36, 48 RSRVD 20 The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger input Open drain output, ...
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FBGA Package Table 2: Signal Descriptions for Standard Interface (Mobile DiskOnChip P3 256Mb 7x10 FBGA Package) Signal Ball No. A[12:11] D7, C7 A[10:8] F6, E6, C6 A[7:4] C2, D2, E2, F2 A[3:0] D1, E1, F1, G1 D[15:14] H7, K7 ...
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Signal Ball No. IRQ# F8 DPD G1 VCC J4 VCCQ J5 VSS G2, J8 RSRVD See Figure The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger input Open drain output, ...
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Multiplexed Interface 2.3.1 Pin/Ball Diagram See Figure 4 and Figure 5 for the Mobile DiskOnChip P3 256Mb pinout/ballout for the multiplexed interface. To ensure proper device functionality, pins/balls marked RSRVD are reserved for future use and should not be ...
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FBGA Package VSS D VSS VSS E VSS VSS F VSS VSS G DPD VSS H CE# OE# J RSRVD AD0 K AD8 ...
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System Interface See Figure 6 for a simplified I/O diagram. CE#, OE#, WE# Host System Bus System Interface Figure 6: Multiplexed Interface Simplified I/O Diagram 16 Mobile DiskOnChip P3 AD[15:0] ID0 LOCK# AVD# Configuration Data Sheet, Rev. 0.3 Mobile ...
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Signal Description Mobile DiskOnChip P3 256Mb TSOP-I and 7x10 FBGA packages support identical signals in the multiplexed interface. The related pin/ball designations are listed in the signal descriptions, presented in logic groups, in Table 3 and Table 4. TSOP-I ...
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Input Signal Pin No. Type VCCQ 37,22 - VCC 12 - VSS 5-11, 14-18, - 13, 25, 36, 48 RSRVD 20 - The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger input Open ...
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FBGA Package Table 4: Signal Descriptions for Multiplexed Interface (Mobile DiskOnChip P3 7x10 FBGA Package) Input Signal Ball No. Type AD[15:14] H7 Multiplexed bus. Address and data signals AD[13:12] H6, J6 AD[11:9] K4, J3, H3 AD[8:6] K2, ...
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Input Signal Ball No. Type VCC J4 - VCCQ J5 VSS G2,J8, - D7,C7,F6,E6, C6,C2,D2,E2 ,F2,D1,E1,F1 RSRVD See Figure The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger ...
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T O HEORY OF PERATION 3.1 Overview Mobile DiskOnChip P3 consists of the following major functional blocks, as shown in Figure 7. *ADDR[0] and DPD are multiplexed on the same ball/pin. Figure 7: Mobile DiskOnChip P3 Simplified Block Diagram, ...
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Bus Control for translating the host bus address, and data and control signals into valid NAND flash signals. • Address Decoder to enable the relevant unit inside the DiskOnChip controller, according to the address range received from the system ...
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Configuration Interface The Configuration Interface block enables the designer to configure Mobile DiskOnChip P3 to operate in different modes. The ID[1:0] signals are used in a cascaded configuration (refer to Section 10.6), the DPD signal is used to enter ...
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One-Time Programmable (OTP) Area The 6KB OTP area is user programmable for complete customization. The user can write to this area once, after which it is automatically and permanently locked. After it is locked, the OTP area becomes read ...
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Download Engine (DE) Upon power-up or when the RSTIN# signal is asserted, the DE automatically downloads the Initial Program Loader (IPL) to the Programmable Boot Block. The IPL is responsible for starting the booting process. The download process is ...
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Flash Architecture Mobile DiskOnChip P3 256Mb consists of two 128Mb flash planes that consist of 1024 blocks each, divided in groups of 32 pages, as follows: • Page – Each page contains 512 bytes of user data and a ...
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Good Unit Good Unit Good Unit Bad Unit ~ ~ Good Unit Good Unit Good Unit Flash Plane 1 27 Internal Bus Aligned Unit Aligned Unit Aligned Unit ~ ~ ~ ~ Aligned Unit Aligned Unit Figure 10: Unaligned Multi-Plane ...
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T X ECHNOLOGY Mobile DiskOnChip P3 enhances performance using various proprietary techniques: • Parallel access to the separate 128Mb flash planes, thereby providing an internal 32-bit data bus. See Section 3.10 for further information. • MultiBurst operation to ...
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Host Internal data transfers /Flash_OE Data transfer from Flash Planes to FIFO External data transfers /DiskOnChip_OE Data transfer from FIFO to Host Note: Mobile DiskOnChip P3 does not support MultiBurst write operations. MultiBurst operation is controlled by 5 ...
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The LATENCY bit is the third bit that must be set in the MultiBurst Mode Control register. When the LATENCY bit is set to 0, the host can latch the first 16-bit data word two clock cycles after CLK0. This ...
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Set the bits in the Interrupt Control register (see Section 8) to enable interrupts on an ECC error and at the end of the DMA operation. 3. Write to the DMA Control register[0] to set the DMA_EN bit, the ...
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H P ARDWARE ROTECTION 5.1 Method of Operation Mobile DiskOnChip P3 enables the user to define two partitions that are protected (in hardware) against any combination of read or write operations. The two protected areas can be configured as ...
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Low-Level Structure of the Protected Area The first five blocks in Mobile DiskOnChip P3 contain foundry information, the Data Protect structures, IPL code, and bad block mapping information. See Figure 12. Bad Block Table and Factory-Programmed UID Data Protect ...
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Block 3 and 4 o Data Protect Structure 1. This structure contains configuration information on one of the two user-defined protected partitions. o IPL Code (2KB). This is the boot code that is downloaded by the DE to the internal ...
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M O ODES OF PERATION Mobile DiskOnChip P3 operates in one of three basic modes: • Normal mode • Reset mode • Deep Power-Down mode The current mode of the chip can always be determined by reading the DiskOnChip ...
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Normal Mode This is the mode in which standard operations involving the flash memory are performed. Normal mode is entered when a valid write sequence is sent to the DiskOnChip Control register and Control Confirmation register. The boot detector ...
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Applications that use Mobile DiskOnChip boot device must ensure that the device is not in Deep Power-Down mode before reading the Boot vector/instructions. This can be done by pulsing RSTIN# to the asserted state and waiting for ...
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T FFS T RUE ECHNOLOGY 7.1 General Description M-Systems’ patented TrueFFS technology was designed to maximize the benefits of flash memory while overcoming inherent flash limitations that would otherwise reduce its performance, reliability and lifetime. TrueFFS emulates a hard ...
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Built-In Operating System Support The TrueFFS driver is integrated into all major OSs, including Symbian, Palm OS, Pocket PC 2002/3, Smartphone 2002/3, Windows CE/NT, Linux (various kernels), Nucleus, and others. For a complete listing of all available drivers, please ...
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To overcome this inherent deficiency, TrueFFS uses M-Systems’ patented wear-leveling algorithm. This wear-leveling algorithm ensures that consecutive writes of a specific sector are not written physically to the same page in the flash. This spreads flash media usage evenly across ...
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Special Features Through I/O Control (IOCTL) Mechanism In addition to standard storage device functionality, the TrueFFS driver provides extended functionality. This functionality goes beyond simple data storage capabilities to include features such as: formatting the media, read/write protection, boot ...
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R D EGISTER ESCRIPTIONS This section describes various Mobile DiskOnChip P3 registers and their functions, as listed in Table 5. Most Mobile DiskOnChip P3 registers are 8-bit, unless otherwise denoted as 16-bit. Address (Hex) 103E 1000/1074 1004 1006 1008 ...
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No Operation (NOP) Register Description: A call to this 16-bit register results in no operation. To aid in code readability and documentation, software should access this register when performing cycles intended to create a time delay. Address (hex): 103E ...
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Bus Lock Register Description: This register provides a mechanism for a CPU to request and hold sole access rights to Mobile DiskOnChip P3 in multiprocessor applications. The following algorithm must be implemented to ensure that only one CPU at ...
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Endian Control Register Description: This 16-bit register is used to control the swapping of the low and high data bytes when reading or writing with a 16-bit host. This provides an Endian- independent method of enabling/disabling the byte swap ...
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DiskOnChip Control Register/Control Confirmation Register Description: These two registers are identical and contain information about the Mobile DiskOnChip P3 operational mode. After writing the required value to the DiskOnChip Control register, the complement of that data byte must also ...
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Device ID Select Register Description cascaded configuration, this register controls which device provides the register space. The value of bits ID[0:1] is compared to the value of the ID configuration input pins/balls. The device whose ID input ...
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Interrupt Control Register Description: This 16-bit register controls how interrupts are generated by Mobile DiskOnChip P3, and indicates which of the following five sources has asserted an interrupt: 0: Flash array is ready 1: Data protection violation 2: Reading ...
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Bit No. 14 EDGE. Selects edge or level triggered interrupts: 0: Specifies level-sensitive interrupts in which the IRQ# output remains asserted until the interrupt is cleared. 1: Specifies edge-sensitive interrupts in which the IRQ# output pulses low and return to ...
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Output Control Register Description: This register controls the behavior of certain output signals. This register is reset by a hardware reset, not by entering Reset mode. Note: When multiple devices are cascaded, writing to this register will affect all ...
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DPD Control Register Description: This register specifies the behavior of the DPD input signal. Address (hex): 107C Bit 7 Bit 6 Read/Write Description PD_OK Reset Value 0 Bit No. 3-0 MODE[0:3]. Controls the behavior of the DPD input: 0000: ...
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DMA Control Register [1:0] Description: These two 16-bit registers specify the behavior of the DMA operation. Address (hex): 1078/107A Bit 7 Bit 6 Read/Write R Description RFU_0 Reset Value 0 Bit 15 Bit 14 Read/Write R Description DMA_EN PAUSE ...
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Read/Write Description Reset Value 0 Bit No. 9-0 NEGATE_COUNT. When the EDGE bit of DMA Control register[ this bit must be programmed to specify the bus cycle in which DMARQ# will be negated as follows: NEGATE_COUNT = ...
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MultiBurst Mode Control Register Description: This 16-bit register controls the behavior of Mobile DiskOnChip P3 during MultiBurst mode read cycles. Address (hex): 101C Bit 7 Bit 6 Read/Write Description Reset Value 0 Bit 15 Bit 14 Read/Write Description Reset ...
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B M OOTING FROM OBILE 9.1 Introduction Mobile DiskOnChip P3 can function both as a flash disk and as the system boot device. Mobile DiskOnChip P3 default firmware contains drivers to enable it to perform as the OS boot ...
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Mobile DiskOnChip P3 can be used as the only disk in the system, with or without a floppy drive, and with or without hard disks. The drive letter assigned depends on how Mobile DiskOnChip P3 is ...
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Non-PC Architectures In non-PC architectures, the boot code is executed from a boot ROM, and the drivers are usually loaded from the storage device. When using Mobile DiskOnChip P3 as the system boot device, the CPU fetches the first ...
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D C ESIGN ONSIDERATIONS 10.1 General Guidelines A typical RISC processor memory architecture is shown in Figure 17. It may include the following devices: • Mobile DiskOnChip P3: Contains the OS image, applications, registry entries, back-up data, user files ...
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Standard NOR-Like Interface Mobile DiskOnChip P3 uses a NOR-like interface that can easily be connected to any microprocessor bus. With a standard interface, it requires 13 address lines, 8 data lines and basic memory control signals (CE#, OE#, WE#), ...
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Multiplexed Interface With a multiplexed interface, Mobile DiskOnChip P3 requires the signals shown in Figure 19 below. 0.1 uF Address/Data AVD# Output Enable Write Enable Chip Enable Reset Chip ID 10.4 Connecting Control Signals 10.4.1 Standard Interface When using ...
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Chip Identification (ID[1:0]) – Connect these signals as shown in Figure 18. Both signals must be connected to VSS if the host uses only one DiskOnChip. If more than one device is being used, refer to Section 10.6 for ...
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Implementing the Interrupt Mechanism 10.5.1 Hardware Configuration To configure the hardware for working with the interrupt mechanism, connect the IRQ# pin/ball to the host interrupt input. Note: A nominal 10 KΩ pull-up resistor must be connected to this pin/ball. ...
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Device Cascading When connecting Mobile DiskOnChip P3 256Mb using a standard interface four devices can be cascaded with no external decoding circuitry. Figure 20 illustrates the configuration required to cascade four devices on the host bus (only ...
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Boot Replacement A typical RISC architecture uses a boot ROM for system initialization. The boot ROM is also required to access Mobile DiskOnChip P3 during the boot sequence in order to load OS images and the device drivers. M-Systems’ ...
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Platform-Specific Issues Following is a description of hardware design issues for major embedded RISC processor families. 10.8.1 Wait State Wait states can be implemented only when Mobile DiskOnChip P3 is designed in a bus that supports a Wait state ...
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Data Access Mode When configured for 8-bit operation, pin/ball IF_CFG should be connected to VSS, and data lines D[15:8] are internally pulled up and may be left unconnected. The controller routes odd and even address accesses to the ...
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Design Environment Mobile DiskOnChip P3 provides a complete design environment consisting of: • Evaluation boards (EVBs) for enabling software integration and development with Mobile DiskOnChip P3, even before the target platform is available. • Programming solutions: o GANG programmer ...
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P S RODUCT PECIFICATIONS 11.1 Environmental Specifications 11.1.1 Operating Temperature Commercial temperature range: Extended temperature range: -40°C to +85°C 11.1.2 Thermal Characteristics Junction to Case (θ 11.1.3 Humidity 10% to 90% relative, non-condensing 11.1.4 Endurance Mobile DiskOnChip P3 is ...
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Capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT Capacitance is not 100% tested. 11.2.3 DC Electrical Characteristics Over Operating Range See Table 10 and Table 11 for DC characteristics for VCCQ ranges 1.65-2.0V and 2.5-3.6V I/O, ...
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Symbol Parameter Maximum low-level output I OLmax current I Input leakage current ILK I Output leakage current IOLK V High-level output voltage OH V Low-level output voltage OL Active supply current VCC+VCCQ pins/balls Standby supply current, I CCS ...
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Timing Specifications 11.3.1 Read Cycle Timing Standard Interface t SU A[12:0] CE# t (CE1) HO OE# WE# D[15:0] Figure 23: Standard Interface, Read Cycle Timing t SU A[12:0] CE# t (CE1) HO OE# WE# D[15:0] Figure 24: Standard Interface ...
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Table 13: Standard Interface Read Cycle Timing Parameters Symbol Description Tsu(A) Address to OE# Tho(A) OE# to Address hold time Tsu(CE0) CE# to OE# setup time Tho(CE0) OE# to CE# hold time Tho(CE1) OE# or WE# to CE# Tsu(CE1) CE# ...
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Write Cycle Timing Standard Interface t SU A[12:0] t (CE1) HO CE# OE# WE# D[15:0] Figure 25: Standard Interface Write Cycle Timing Table 14: Standard Interface Write Cycle Parameters Symbol Description T (A) Address to WE# SU Tho(A) WE# ...
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Read Cycle Timing Multiplexed Interface AVD# t (AVD) SU AD[15:0] CE# t (CE1) HO OE# WE# Figure 26: Multiplexed Interface Read Cycle Timing Table 15: Multiplexed Interface Read Cycle Parameters Symbol Description tsu(AVD) Address to AVD# tho(AVD) Address to ...
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Write Cycle Timing Multiplexed Interface AVD# t (AVD) SU AD[15:0] t (CE1) HO CE# OE# WE# Figure 27: Multiplexed Interface Write Cycle Timing Table 16: Multiplexed Interface Write Cycle Parameters Symbol Description tsu(AVD) Address to AVD# tho(AVD) Address to ...
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Read Cycle Timing MultiBurst In Figure 28, the MultiBurst Control register values are: LATENCY=0, LENGTH=4, CLK_INV=0. t (CLK1) W CLK t (OE0-CLK0) HO OE# t (OE0-CLK1 (OE0-CLK1) SU D[15:0] (HOLD=0) D[15:0] (HOLD=1) Insert LATENCY clock cycles Note: ...
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Symbol OE 1,3 driven t (D) OE Hi-Z delay HIZ 1. CE# may be asserted any time before or after OE# is asserted. If CE# is asserted after OE#, all timing relative to OE# asserted will ...
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VCC = 2.5V VCCQ = 1.65 or 2.5V VCC RSTIN# BUSY# A[12:0] CE#, OE# (WE (Read cycle) AVD# (Muxed Mode Only) DPD (A[0]) Symbol T (VCC-RSTIN) VCC/VCCQ stable to RSTIN# REC T (RSTIN) RSTIN# asserted pulse width ...
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Interrupt Timing IRQ# Symbol Tw(IRQ#) IRQ# asserted pulse width (Edge mode) 11.3.9 DMA Request Timing OE#/CE# DMARQ# Note: Polarity of DMARQ# may be inverted based on the NORMAL bit of DMA Control Register[0]. Symbol Tw(DMARQ#) DMARQ# asserted pulse width ...
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Mechanical Dimensions TSOP-I dimensions: 20.0±0. 12.0±0. 1.2±0.10 mm Figure 32: Mechanical Dimensions TSOP-I Package 80 Data Sheet, Rev. 0.3 Mobile DiskOnChip P3 93-SR-009-8L ...
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FBGA dimensions: 7.0±0. 10.0±0. 1.2±0.10 mm Ball pitch: 0.8 mm Figure 33: Mechanical Dimensions 7x10 FBGA Package 81 Data Sheet, Rev. 0.3 Mobile DiskOnChip P3 93-SR-009-8L ...
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... DiskOnChip P3 TSOP-I 5832 - DiskOnChip P3 FBGA (7x10) Refer to Table 21 for combinations currently available and the associated order numbers. Ordering code MD5811-d256-V3Q18 MD5811-d256-V3Q18-X MD5811-d256-V3Q18-P MD5811-d256-V3Q18-X-P MD5832-d256-V3Q18-X MD5832-d256-V3Q18-X-P MD5832-d00-DAISY MD5811-d256-MECH MD5832-d256-MECH 82 MDxxxx-Dxxx-xxx-T-C Capacity D- MByte d- Mbit xxx - Value Supply Voltage V3Q18 - 3.3V core, 1.8V I/O Figure 34: Ordering Information Structure ...
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... ONTACT S USA M-Systems Inc. 8371 Central Ave, Suite A Newark CA 94560 Phone: +1-510-494-2090 Fax: +1-510-494-5545 Japan M-Systems Japan Inc. Asahi Seimei Gotanda Bldg., 3F 5-25-16 Higashi-Gotanda Shinagawa-ku Tokyo, 141-0022 Phone: +81-3-5423-8101 Fax: +81-3-5423-8102 Taiwan M-Systems Asia Ltd. Room No. 133 Sec. 3 ...