MC-4516CD641PS-A10 NEC, MC-4516CD641PS-A10 Datasheet
MC-4516CD641PS-A10
Manufacturer Part Number
MC-4516CD641PS-A10
Description
16M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE SO DIMM
Manufacturer
NEC
Datasheet
1.MC-4516CD641PS-A10.pdf
(16 pages)
Document No. M14014EJ5V0DS00 (5th edition)
Date Published February 2000 NS CP(K)
Printed in Japan
Description
module (Small Outline DIMM) on which 8 pieces of 128M SDRAM: PD45128163 are assembled.
mounting technology on the printed circuit board.
Features
MC-4516CD641ES-A80
MC-4516CD641ES-A10
MC-4516CD641PS-A80
MC-4516CD641PS-A10
The MC-4516CD641ES and MC-4516CD641PS are 16,777,216 words by 64 bits synchronous dynamic RAM
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
Decoupling capacitors are mounted on power supply line for noise reduction.
16,777,216 words by 64 bits organization
Clock frequency and access time from CLK
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0, BA1 (Bank Select)
Programmable burst-length (1, 2, 4, 8 and Full Page)
Programmable wrap sequence (Sequential / Interleave)
Programmable /CAS latency (2, 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
Single 3.3 V 0.3 V power supply
LVTTL compatible
4,096 refresh cycles/64 ms
Burst termination by Burst Stop command and Precharge command
144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)
Unbuffered type
Serial PD
Part number
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
MC-4516CD641ES, 4516CD641PS
/CAS latency
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
The mark • • • • shows major revised points.
16M-WORD BY 64-BIT
DATA SHEET
Clock frequency (MAX.)
100 MHz
100 MHz
125 MHz
100 MHz
125 MHz
100 MHz
77 MHz
77 MHz
MOS INTEGRATED CIRCUIT
Access time from CLK (MAX.)
6 ns
6 ns
6 ns
7 ns
6 ns
6 ns
6 ns
7 ns
©
1999
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