PLCD5584 Siemens Semiconductor, PLCD5584 Datasheet - Page 8

• Manufacturer Part Number: PLCD5584
• Description: (PLCD5580 - PLCD5584) 5x5 Dot Matrix Parallel Input Alphanumeric Intelligent Display
• Manufacturer: Siemens Semiconductor

Block Diagram
Functional Description
The PLCD558X block diagram is comprised of the following
major blocks and registers.
Display Memory consists of a 8x8 bit RAM block. Each of
the eight 8-bit words holds the 7-bit ASCII data (bit D0-D6).
The 8th bit, D7 selects 1 of the 2 pages of character ROM.
D7=0 selects Page 1 of the ROM and D7=1 selects Page 2 of
the ROM. A3=1.
RST can be used to initialize display operation upon power
up or during normal operation. When activated, RST will clear
the Flash RAM and Control Word Register (00H) and reset the
internal counter. All eight display memory locations will be set
to 20H to show blanks in all digits.
set (D0=1)or reset (D0=0) flashing of the character
addressed by A0–A2.
The 1x8 bit Control Word RAM is loaded with attribute data
if A3=0.
The Control Word Logic decodes attribute data for proper
implementation.
Character ROM is designed for two pages of 128 characters
each. Both pages of the ROM are Mask Programmable for
custom fonts. On the standard product page one contains
standard ASCII, selected European characters and some sci-
entific symbols. Page two contains Katakana characters,
more European characters, avionics, and other graphic sym-
bols.
FL pin enables access to the Flash RAM. The Flash RAM will
CLKSEL
CLK I/O
RST
D6
D5
D4
D3
D2
D1
D0
D7
Address
Lines
A0 A1 A2 A3 WR CE
8 x 8 Bits
OSC
Display
Memory
Address Decoder
+ 32
Counter
Flash RAM
(8 x 1 Bit)
Control Word
Decode Logic
+ 7
Counter
7 Bit ASCII
Code
Row Control Logic
& Row Drivers
FL
Mux
Rate
Rows 0 to 9
+ 128
Counter
Blink
Rate
128x7 Bit
ASCII
Character
Decode
(4.48K Bits)
ROM 1
Row Decoder
0
1
Timing and
Control Logic
128x7 Bit
ASCII
Character
Decode
(4.48K Bits)
ROM 2
2–138
2
The Clock Source could either be the internal oscillator
(CLKSEL=1) of the device or an external clock (CLKSEL=0)
could be an input from another PLCD211X display for the
synchronization of blinking for multiple displays.
The Display Multiplexer controls the Row Drivers so no
additional logic is required for a display system.
The Display has eight digits. Each digit has 25 LEDs clus-
tered into a 5x5 dot matrix.
Theory of Operation
The PLCD558X Programmable display is designed to work
with all major microprocessors. Data entry is via an eight bit
parallel bus. Three bits of address route the data to the
proper digit location in the RAM. Standard control signals like
WR and CE allow the data to be written into the display.
D0–D7 data bits are used for both ASCII and control word
data input. A3 acts as the mode selector. If A3=0, D0–D7
load the RAM with control word data. If A3=1, D0–D7 will
load the RAM with ASCII and page select data. In the later
mode, D7=0 selects Page 1 of Character ROM and D7=1
selects Page 2 of Character ROM.
For normal operation FL pin should be held high. When FL is
held low, Flash RAM is accessed to set character blinking.
The seven bit ASCII code is decoded by the Character ROM
to generate Column data. Twenty columns worth of data is
sent out each display cycle and it takes fourteen display
cycles to write into eight digits.
The rows are being multiplexed in two sets of five rows each.
The internal timing and control logic synchronizes the turning
on of rows and presentation of column data to assure proper
display operation.
DISPLAY
3
4
Column
Data
5
6
7
Master
Slave
Latches
Digit
0 to 8
Columns 0 to 19
Column
Drivers for
Digit 0 to 8
PLCD5580/1/2/3/4