ISL6884 Intersil Corporation, ISL6884 Datasheet
ISL6884
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ISL6884 Summary of contents
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... Data Sheet CCFL Brightness Controller ISL6884 controls Pulse Width Modulated Dimming for inverters to supply power Cold Cathode Fluorescent Lamps (CCFL) for back lighting in large LCD displays. The ISL6884 brightness controller provides an I for dimming control, enable, status, and brightness balance. ...
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... Block Diagram VDD GND EN I2C ENABLE DPWM SYNC PLL1 GNDPLL SDA I2C interface SCL 2 ISL6884 BGREF POR ENAB fault timer PWM DIMMING PLL 8 CH DPWM GEN OSC BRIGHTNESS STATUS ENABLE (I2C) CCFL Brightness Controller REGCAP 2.5V REG STATUS LAMP ON DPWM_8 DPWM_7 DPWM_6 ...
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... Simplified System Diagram - Central Controller and Multiple Local Controllers ISL6884 CENTRAL SCL SDA CONTROLLER 3 ISL6884 SYSTEM I2C MASTER DRIVE ISL6882 IFB LOCAL VFB DPWM CONTROLLER PHASE MODULATION OUT DRIVE ISL6882 IFB LOCAL VFB DPWM CONTROLLER PHASE MODULATION OUT DRIVE ISL6882 IFB ...
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... ISL6884 Application Schematic external hardware enable Use these parts to adjust the internal DPWM oscillator frequency 3300 2200 1uF 0.47uF 73.2K This is the LPF for the DPWM PLL 4 ISL6884 LAMPON output from ISL6882 LAMP_ON 1 TESTEN 2 GNDPLL 3 PLL1 ISL6884 DPWM_SYNC 6 OSCTEST 7 SCL 8 SDA ...
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... V In Low V In High Schmitt Trigger Input Hysteresis V Out Low SDA, SCL Rise Time SDA, SCL Fall Time 5 ISL6884 Thermal Information Thermal Resistance (Typical, Notes SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Information Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s 300° ...
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... They should be left unconnected in normal operation. 1.1 1.3 MIN TYP MAX UNITS - 160 - Hz 120 160 200 Hz - 150 - 100 % 0.7*VDD - - 0.3*VDD 500 500 registers clock line. The ISL6884 enable or disable the inverters, set 2 C. FN9265.0 March 9, 2006 2 C ...
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... FLT_TOUT - Fault Timer Time Out Setting. This register controls the response of the ISL6884 to a logic low input on the LAMPON pin (indicating that one or more lamps is NOT ON). A value between 0X01 and 0XFF in the FLT_TOUT register will set the time that ISL6884 will operate with a low signal at the LAMPON pin (fault time out) ...
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... Master Enable, This signal is AND’ed with the en pin to create the enable for the PWM dimming output. 0x2a POR 0 0 ch_en Individual Channel Enables for each DPWM output. 0x2b b7 b6 POR 0 0 flt_tout Fault Timer Time Out Setting. 8 ISL6884 DESCRIPTION BIT 5 LABEL BIT 4 LABEL BIT 3 LABEL POR VALUE POR VALUE POR VALUE ...
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... POR 1 1 dc_min Duty Cycle Minimum Setting. See DPWM Document for description. Caution! Changing this register from its default value may result in unpredictable behavior 9 ISL6884 DESCRIPTION BIT 5 LABEL BIT 4 LABEL BIT 3 LABEL POR VALUE POR VALUE POR VALUE b5 b4 ...
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... Caution! Changing this register from its default value may result in unpredictable behavior 0x3A POR ISL6884 DESCRIPTION BIT 5 LABEL BIT 4 LABEL BIT 3 LABEL POR VALUE POR VALUE POR VALUE ...
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... S START CONDITION FIGURE 1. START AND STOP WAVEFORMS 11 ISL6884 Data Validity The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. Refer to Figure 2. ...
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... I C Transactions Between the System Master and the ISL6884 Below are typical transactions between the system master and the ISL6884. WRITING TO ONE REGISTER IN ISL6884 SCL SDA ISL6884 REGISTER ADDRESS DEVICE ADDRESS WRITING N CONSECUTIVE REGISTERS TO ISL6884 SCL SDA ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 ISL6884 M20. ...