SG6902 Fairchild Semiconductor, SG6902 Datasheet - Page 15

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SG6902

Manufacturer Part Number
SG6902
Description
Green-Mode PFC / Flyback-PWM Controller
Manufacturer
Fairchild Semiconductor
Datasheet
www.DataSheet4U.com
Green-Mode PFC / Flyback-PWM Controller
Line-Voltage Detection (VRMS)
Figure 2 shows a resistive divider with low-pass filtering
for line-voltage detection on the VRMS pin. The V
voltage is used for the PFC multiplier, brownout
protection, and range control.
For brownout protection, the SG6902 is disabled with
195ms delay time if the voltage V
For PFC multiplier and range control, refer to the sections
below for details.
FIG.2 Line-Voltage Detection Circuit
PFC Output Voltage Control (RANGE)
For a universal input (90V
applying active boost PFC and flyback as a second stage,
the output voltage of PFC is usually designed around
250V at low line and 390V at high line. This is to improve
efficiency at low-line input. In SG6902, the RANGE pin
(open-drain structure) is used for the two-level output
voltage setting.
Figure 3 shows the RANGE output that programs the PFC
output voltage. The RANGE output is shorted to ground if
the V
(open) and the V
output voltages can be designed using below equations:
© System General Corp.
Version 1.3.1 (IAO33.0022.B3)
Range
Range
RMS
=
=
Open
Ground
voltage exceeds 1.95V while high impedance
V
RMS
O
V
=
O
R
=
voltage drops below 1.6V. The
A
R
R
+
A
AC
B
(
R
R
+
B
B
~ 264V
(
R
//
×
B
R
3
RMS
//
V
C
R
)
C
drops below 0.8V.
AC
)
) power supplies
×
3
V
----
(3)
RMS
- 15 -
FIG.3 Range Control Two-Level Output Voltage
Interleave Switching and Green-Mode
Operation
The SG6902 uses interleaved switching to synchronize
the PFC and flyback stages, which reduces switching
noise and spreads the EMI emissions. Figure 4 shows
off-time, T
gate drive and the turn-on of the PWM.
The off-time T
decreasing of the voltage level of FBPWM. Therefore, the
PWM switching frequency is continuously decreased to
reduce switching losses. To further reduce power losses
under extra light-load conditions, the PFC stage is turned
off with a 650ms delay time.
FIG.4 Interleaved Switching Pattern
OFF
www.sg.com.tw • www.fairchildsemi.com
, inserted between the turn-off of the PFC
OFF
is increased in response to the
Product Specification
September, 2007
SG6902

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