D75108CW NEC, D75108CW Datasheet - Page 56

• Manufacturer Part Number: D75108CW
• Description: Search -----> UPD75108CW
• Manufacturer: NEC

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56
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE
(T
DATA RETENTION TIMING
a
Data Retention Supply
Voltage
Data Retention Supply
Current*
Release Signal Set Time
Oscillation Stabilization
Wait Time*
*1: The current flowing through internal pull-up resistor, power-ON reset circuit (mask option), and
BTM3
RESET
2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent
3: Depends on the setting of the basic interval timer mode register (BTM) as follows:
= –40 to +85 C)
–
–
–
–
V
V
comparator circuit is not included
unstable operation when oscillation is started.
DD
DD
Standby release signal
Parameter
(interrupt request)
1
BTM2
2
0
0
1
1
BTM1
STOP instruction
execution
STOP instruction execution
0
1
0
1
V
I
t
t
BTM0
Symbol
DDDR
SREL
WAIT
DDDR
0
1
1
1
(releasing STOP mode by RESET)
Wait time ( ): f
2
2
2
2
20
17
15
13
V
Released by RESET
Released by interrupt request
/f
/f
/f
/f
DDDR
XX
XX
XX
XX
(approx. 250 ms)
(approx. 31.3 ms)
(approx. 7.82 ms)
(approx. 1.95 ms)
= 2.0 V
XX
Data retention mode
Data retention mode
Conditions
STOP mode
STOP mode
= 4.19 MHz
V
V
DDDR
DDDR
Internal reset operation
MIN.
PD75104, 75106, 75108
2.0
0
t
t
SREL
SREL
2
TYP.
0.1
17
*
HALT mode
HALT mode
/f
3
X
t
t
WAIT
WAIT
MAX.
6.0
10
Unit
Operation
mode
Operation
mode
ms
ms
V
A
s