D75208CW NEC, D75208CW Datasheet
D75208CW
Related parts for D75208CW
D75208CW Summary of contents
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... For remote controlled reception Product with an on-chip PROM : PD75P216A, PD75P218 (on-chip EPROM : WQFN package) ORDERING INFORMATION Ordering Code PD75208CW- PD75208GF- -3BE Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. ...
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LIST OF FUNCTIONS Item Instruction execution time On-chip memory ROM RAM General register Input/output port ® FIP dual-function pin included FIP dedicated pin excluded FIP controller/driver Timer Serial interface Vectored interrupt Test input System clock oscillator Standby function Mask ...
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PIN CONFIGURATION (TOP VIEW) ....................................................................................... 5 2. BLOCK DIAGRAM .................................................................................................................... 6 3. PIN FUNCTIONS ...................................................................................................................... 7 3.1 PORT PINS .................................................................................................................................... 7 3.2 NON-PORT PINS .......................................................................................................................... 8 3.3 PIN INPUT/OUTPUT CIRCUIT LIST ............................................................................................ 9 3.4 UNUSED PINS TREATMENT .................................................................................................... ...
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ELECTRICAL SPECIFICATIONS ............................................................................................ 38 13. CHARACTERISTIC CURVES .................................................................................................. 50 14. PACKAGE INFORMATION .................................................................................................... 54 15. RECOMMENDED SOLDERING CONDITIONS ..................................................................... 57 APPENDIX A DEVELOPMENT TOOLS .................................................................................... 58 APPENDIX B RELATED DOCUMENT ....................................................................................... 59 4 PD75208 ...
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PIN CONFIGURATION (TOP VIEW P41 52 P42 53 P43 54 PPO ...
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BASIC INTERVAL TIMER INTBT TI0/P13 TIMER/EVENT COUNTER #0 INTT0 TIMER/PULSE GENERATOR PPO INTTPG SI/P03 SERIAL SO/P02 INTERFACE SCK/P01 INTSIO INT0/P10 INT1/P11 INTERRUPT INT2/P12 CONTROL INT4/P00 WATCH TIMER BUZ/P23 CY PROGRAM ALU COUNTER(13) ROM PROGRAM MEMORY DECODE 8064 8 BITS AND ...
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PIN FUNCTIONS 3.1 PORT PINS Dual- Pin Name I/O Function Pin P00 Input INT4 P01 Input/output SCK P02 Input/output SO P03 Input SI P10 INT0 Input P11 INT1 P12 INT2 P13 TI0 P20 Input/ ––– output P21 ––– ...
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... Edge-detected testable input (rising edge detection). Fixed frequency output (for buzzer or system clock trimming). Crystal/ceramic connect pin for main system clock oscillation. External clock input to X1 and its inverted clock input to X2. Crystal connect pin for subsystem clock oscillation. ...
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PIN INPUT/OUTPUT CIRCUIT LIST TYPE CMOS-Specified Input Buffer TYPE B IN Schmitt Trigger Input Having Hysteresis Characteristics TYPE D data output disable Push-Pull Output which can be Set to Output High Impedance (with Both P-ch ...
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... V when there is no on- LOAD chip load resistor 10 Recommended Connection Connect Connect Connect Input state : Connect Output state : Leave open Leave open Connect Leave open Connect Connect ...
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... P50 and XT2 pins and the correct watch functions cannot be achieved (the watch becomes fast necessary to allow the P50 pin signal to switch between high and low, mount an external capacitor to the P50 pin as shown below. is applied to one of these pins. If noise larger than ...
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ARCHITECTURE AND MEMORY MAP OF THE PD75208 The PD75208 has three architectural features: • Bank configuration of data memory • Bank configuration of general registers: 8 • Memory mapped I/O Fig. 4-1 and 4-2 show the memory maps ...
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General Static RAM (497 4) Fig. 4-2 Data Memory Map General Register Area Stack Area ...
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PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS The PD75208 has the following three types of I/O port: • 8 CMOS input ports • 20 CMOS I/O ports • 4 P-ch open-drain high-voltage, large-current output ports Total: 32 ports Port Name ...
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CLOCK GENERATOR Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control register (SCC). The main system clock or subsystem clock can be selected. The instruction execution time is variable. ...
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BASIC INTERVAL TIMER The basic interval timer has the following functions: • Interval timer operation to generate reference time • Watchdog timer application to detect inadvertent program loop • Wait time select and count upon standby mode release ...
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WATCH TIMER The PD75208 incorporates one channel of watch timer. The watch timer has the following functions: • Sets the test flag (IRQW) at 0.5 sec intervals. The standby mode can be released by IRQW. • 0.5 second ...
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TIMER/EVENT COUNTER The PD75208 incorporates one channel of timer/event counter. The timer/event counter has the following functions: • Program interval timer operation • Event counter operation • Count state read function TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 Input ...
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... PWM pulse output to the PPO pin (Used as a digital-to-analog converter and applicable to tuning) • Fixed time interval ( If pulse output is not necessary, the PPO pin can be used as a 1-bit output port. Note If the STOP mode is set while the timer/pulse generator is in operation, erroneous operation may result. ...
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Fig. 5-6 Timer/Pulse Generator Block Diagram (PWM Pulse Generate Mode) TPGM3 TPGM1 f 1/2 x Frequency Divider 5.7 SERIAL INTERFACE The serial interface has the following functions: • Clock synchronous 8-bit send/receive operation (simultaneous send/receive) • Clock synchronous 8-bit ...
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P03/SI SIO0 Shift Register (8) *1 P02/SO P01/SCK * 1. CMOS output and N-ch open-drain output switchable output buffer. 2. Instruction execution Fig 5-7 Serial Interface Block Diagram Internal Bus 8 SIO7 SIO SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 ...
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FIP CONTROLLER/DRIVER The on-chip FIP controller/driver has the following functions: • Generates the segment and digit signals by automatically reading the display data memory executing DMA operation. • Can select total of 26 display devices ...
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POWER-ON FLAG (MASK OPTION) The power-on flag (PONF) is automatically set (1) when the power-on reset circuit is activated and the power- on reset signal is generated. (See Fig. 8-1 Reset Signal Generator) The PONF is mapped at ...
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Fig. 6-1 Interrupt Control Circuit Block Diagram 2 2 IM1 IM0 Interrupt Enable Flag (IE INT IRQBT BT Both Edges INT4 IRQ4 Detection /P00 Circuit Edge INT0 IRQ0 * Detection /P10 Circuit Edge INT1 IRQ1 * Detection /P11 Circuit INTSIO ...
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STANDBY FUNCTIONS Two standby modes (STOP mode and HALT mode) are available for the PD75208 to decrease power consump- tion in the program standby mode. Set instruction System clock when set Clock oscillator Basic interval timer Serial interface ...
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INSTRUCTION SET (1) Operand identifier and description Enter an operand in the operand column of each instruction using the description method relating to the operand identifier of the instruction (refer to RA75X Assembler Package User's Manual, Language (EEU-730) ...
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Legend for operation description register; 4-bit accumulator register register register register register register register ...
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Description of symbols in the addressing area column * MBE • MBS (MBS = MBE = (00H to 7FH) MB ...
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Mnemonic Operands Note 1 MOV A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL– A, @rpa1 XA, @HL @HL, A @HL mem XA, mem mem, A mem reg ...
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Note Mnemonic Operand MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' ...
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Note 1 Mnemonic Operands RORC A A NOT reg INCS rp1 @HL mem reg DECS rp' reg, #n4 SKE @HL, #n4 A, @HL XA, @HL A, reg XA, rp' SET1 CY CY CLR1 CY SKT CY NOT1 Note 1. ...
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Note Mnemonic Operands SET1 mem.bit fmem.bit pmem.@ mem.bit mem.bit CLR1 fmem.bit pmem.@L @H+mem.bit SKT mem.bit fmem.bit pmem.@L @H+mem.bit SKF mem.bit fmem.bit pmem.@L @H+mem.bit SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit CY, fmem.bit OR1 ...
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Note Mnemonic Operands CALL !addr CALLF !faddr RET RETS RETI PUSH rp BS POP PORTn * XA, PORTn OUT PORTn PORTn, XA HALT STOP NOP SEL RBn MBn * ...
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Note Mnemonic Operands GETI * taddr * TBR and TCALL instructions are assembled pseudo-instructions to define the GETI instruction table. Note Instruction Group 34 No. of Machine Operation Bytes Cycle 1 3 • TBR instruction PC (taddr) +(taddr+1) 12–0 ...
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MASK OPTION SELECTION The PD75208 has the following mask options enabling or disabling on-chip components. (1) Pin Pin P60 to P63 T0/T9 T10/PH3 to T13/PH0 T14/S11, T15/S10 XT1, XT2 Note system not ...
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APPLICATION BLOCK DIAGRAM 11.1 VCR TIMER TUNER Main Power Supply Power Failure Detection LPF Electronic Tuner Tape Count Pulse Tape Up/Down SCK System Controller SO Microcomputer SI PD75104/75106 EEPROM™ PD6252 36 + Super Capacitor ...
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COMPACT DISK PLAYER SIO Servo Control IC Loading Circuit BZ 11.3 ECR Main Power Supply Power Failure Detection RAM Printer T0–T15 16 SCK SI/SO Fluorescent Display Panel (FIP) S0–S11 12 PD75208 PORT6 BUZ INT0 ...
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ( PARAMETER SYMBOL V DD Power supply voltage V LOAD V PRE Input voltage Output voltage V OD Output current high I OH Output current low ...
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... Calculation of total loss Design so that the sum of the following three power consumption values for the PD75208CW/GF will be less than the total loss P (It is recommended to use the system with less of the rating). T CPU loss Output pin loss Pull-down register loss : Power loss due to a pull-down resistor incorporated in the display output pin ...
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MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = – RESONATOR RECOMMENDED CIRCUIT X1 X2 Ceramic resonator Crystal resonator External clock PD74HCU04 * 1. Resonators are shown in the following page. ...
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CAPACITANCE ( PARAMETER Input capacitance Except display output Output capacitance Display output Input /output capacitance RECOMMENDED OSCILLATOR CONSTANTS MAIN SYSTEM CLOCK : CERAMIC RESONATOR (Ta = –40 to +85 C) MANUFACTURER PRODUCT NAME Murata ...
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DC CHARACTERISTICS (Ta = – PARAMETER SYMBOL V V Input voltage high Input Voltage low V V Output voltage high V Output voltage low V I LIH1 Input leakage current high I ...
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... RD9. 1EL V PRE LOAD V SS TEST CONDITIONS DDH DDL off DDPR off PD75208 +5 V RD9. 1EL : Zener Diode (NEC) Zener Voltage = 8.29 to 9.30 V –30 V MIN. TYP. MAX. UNIT 4.5 6.0 0 100 DDH V DDL ...
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AC CHARACTERISTICS (Ta = – PARAMETER SYMBOL CPU clock cycle time (minimum instruction t execution time = 1 machine cycle) *1 TI0 input frequency t TI0 input high and low- level widths t SCK ...
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... CPU clock ( ) cycle time is determined by the oscillator frequency of the connected resonator, the system clock control register (SCC) and the processor clock control register (PCC). The cycle time t characteristics for power supply voltage CY V when the main system clock is in operation is DD shown below ...
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AC Timing Measurement Values (Except X1 and XT1 Inputs) Clock Timing X1 Input XT1 Input TI0 Timing TI0 46 0.75V DD Test Points 0. XTL XTH 1/f TI ...
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Serial Transfer Timing SCK SI SO Interrupt Input Timing INT0,1,2,4 RESET Input Timing RESET t KCY SIK KSI Input Data t KSO Output Data t t INTL INTH t RSL PD75208 47 ...
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DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to +85 C) PARAMETER SYMBOL Data retention power V supply voltage Data retention power I DDDR supply current *1 Release signal set time t SREL ...
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Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal STOP Instruction Execution Standby Release Signal (Interrupt Request) HALT Mode STOP Mode Data Retention Mode t V SREL DDDR PD75208 Operating Mode t WAIT 49 ...
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CHARACTERISTIC CURVES 5000 1000 500 100 Remarks Values of the processor clock control register (PCC) is indicated in parenthesis 4.19 MHz ...
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–20 – –10 – (Ports ...
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–20 –15 –10 – (Ports 2.7 V ...
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(T0 to T15 – PRE V – PRE ...
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PACKAGE INFORMATION 64 PIN PLASTIC SHRINK DIP (750 mil NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to ...
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PIN PLASTIC QFP (14 20 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition ...
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... Care is needed since the metal cap is con- 2. Care is needed since the lead of the base is 3. The lead length is not stipulated since the Bottom View PD75208 0.15 nected to pin 26 and set to the positive power supply level. formed obliquely. cutting of the lead ends is not progress- controlled. ...
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... Pin part heating * For the storage period after dry-pack decompression storage conditions are max RH. Note Use of more than one soldering method should be avoided (except in the case of pin part heating). PD75208CW- : 64-pin plastic shrink DIP (750 mil) Soldering Method Wave soldering Solder bath temperature: 260 C or below , Duration: 10 sec ...
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... Emulation probe for the PD75216AGF. A 64-pin conversion socket, the EV-9200G-64, is attached to the probe. EV-9200G-64 PG-1500 PROM programmer PA-75P216ACW PROM programmer adapter for the PD75P216ACW and PD75P218CW. Connected to the PG-1500. PA-75P218GF PROM programmer adapter for the PD75P218GF. Connected to the PG-1500. PA-75P218KB PROM programmer adapter for the PD75P218KB. Connected to the PG-1500. ...
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... Document Name PACKAGE MANUAL SMD SURFACE MOUNT TECHNOLOGY MANUAL QUALITY GRADES ON NEC SEMICONDUCTOR DEVICES NEC SEMICONDUCTOR DEVICE RELIABILITY/QUALITY CONTROL SYSTEM ELECTROSTATIC DISCHARGE (ESD) TEST GUIDE TO QUALITY ASSURANCE FOR SEMICONDUCTOR DEVICES Note The above documents may be revised without notice. Use the latest versions when you design an application system ...
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... Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. ...
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PD75208 61 ...
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... If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance ...