D75208CW NEC, D75208CW Datasheet - Page 15

• Manufacturer Part Number: D75208CW
• Description: Search -----> UPD75208
• Manufacturer: NEC

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5.2
register (SCC).
* Instruction execution
Remarks
Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control
The main system clock or subsystem clock can be selected.
The instruction execution time is variable.
• 0.95 s, 1.91 s, 15.3 s (main system clock: 4.19 MHz)
• 122 s (subsystem clock: 32.768 kHz)
CLOCK GENERATOR
HALT*
STOP*
1.
2.
3.
4.
5.
6.
7.
4
f
f
f
PCC: Processor clock control register
SCC: System clock control register
1 clock cycle (t
12. ELECTRICAL SPECIFICATIONS.
X
XT
XX
= CPU clock
= Main system clock frequency
PCC2 and
PCC3
Clear
= Subsystem clock frequency
= System clock frequency
SCC3
SCC0
PCC0
PCC1
PCC2
PCC3
SCC
PCC
XT1
XT2
X2
X1
Main System
Subsystem
Generator
Generator
CY
Clock
Clock
) of
Oscillation
Stop
Fig. 5-1 Clock Generator Block Diagram
STOP F/F
Q
is 1 machine cycle of an instruction. For t
f
f
X
XT
R
S
Watch Timer
Timer/Pulse
Generator
f
XX
1/2 1/6
Frequency Divider
1/8 to 1/4096
HALT F/F
S
R
CY
Q
, see ”AC Characteristics“ in
• FIP Controller
• Basic Interval Timer (BT)
• Timer/Event Counter
• Serial Interface
• Watch Timer
• INT0 Noise Eliminator
Wait Release Signal from BT
RES Signal (Internal Reset)
Standby Release Signal from
Interrupt Control Circuit
• CPU
• INT0 Noise Eliminator
• INT1 Noise Eliminator
Frequency
Divider
1/4
PD75208
15