SM55161A Austin Semiconductor, SM55161A Datasheet - Page 29

• Manufacturer Part Number: SM55161A
• Description: 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM
• Manufacturer: Austin Semiconductor

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TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (continued)
NOTE:
1. Timing measurements are referenced to V
2. Cycle time assumes tt = 3 ns.
3. In a read-modify-write cycle, t
4. In a read-modify-write cycle, t
5. The minimum value is measured when t
6. Either t
7. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.
8. CBR refresh operation only.
9. Read-modify-write operation only.
10. TRG\ must disable the output buffers prior to applying data to the DQ pins.
11. The maximum value is specified only to assure RAS\ access time.
12. Real-time-load transfer read or late-load-transfer read cycle only.
13. Early-load-transfer read cycle only.
14. Full-register-(read) transfer cycles only.
15. Switching times for QSF output are measured with a load equivalent to one TTL load and 30 pF, and the output reference level is
Delay time, RAS\ high to last (most significant) rising edge of SC
before boundary switch during split-register-transfer read cycles
Delay time, CASx\ low to TRG\ high in read-time-transfer read
cycles
Delay time, column address to first SC in early-load-transfer read
cycles
Delay time, column address to TRG\ high in real-time-transfer read
cycles
Delay time, data to CASx\ low
Delay time, data to TRG\ low
Delay time, last (most significant) rising edge of SC to RAS\ low
before boundary switch during split-register-transfer read cycles
Delay time, last (127 or 255) rising edge of SC to QSF switching at
the boundary during split-register-transfer read cycles
Delay time, CASx\ low to QSF switching in transfer-read cycles
Delay time, TRG\ high to QSF switching in transfer-read cycles
Delay time, RAS\ lwo to QSF switching in transfer-read cycles
Refresh time interval, memory
Transition time
SMJ55161A
Rev. 1.6 03/05
low time [t
low time [t
V
OH
/ V
h(RHrd)
OL
w(CL)
w(RL)
= 2 V/0.8 V.
or t
].
].
d(CHrd)
Austin Semiconductor, Inc.
must be satisfied for a read cycle.
PARAMETER
d(CLWL)
d(RLWL)
and t
and t
d(RLCL)
IL
su(WCH)
su(WRH)
MAX and V
is set to t
must be observed. Depending on the transition times, this can require additional CASx\
must be observed. Depending on the transition times, this can require additional RAS\
15
d(RLCL)
IH
MIN.
15
15
15
MIN as a reference.
29
SYMBOL
t
t
t
t
t
t
d(GHQSF)
t
t
d(SCQSF)
d(CLQSF)
d(RLQSF)
t
d(RHMS)
d(CAGH)
d(CASH)
t
t
d(MSRL)
d(CLTH)
t
d(DCL)
d(DGL)
rf(MA)
t
t
MIN MAX MIN MAX MIN MAX
20
17
25
20
20
0
0
3
-70
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
25
30
25
70
25
8
20
15
28
20
20
0
0
3
-75
28
33
28
73
25
8
20
15
30
20
20
0
0
3
-80
Production
30
35
30
75
25
SM55161A
8
UNIT
VRAM
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1