80C196NU Intel Corporation, 80C196NU Datasheet - Page 17

• Manufacturer Part Number: 80C196NU
• Description: COMMERCIAL CHMOS MICROCONTROLLER
• Manufacturer: Intel Corporation

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BHE#
BREQ#
CLKOUT
CS5#:0
EA#
PRELIMINARY
Name
Type
O
O
O
O
I
Byte High Enable
During 16-bit bus cycles, this active-low output signal is asserted for word reads
and writes and high-byte reads and writes to external memory. BHE# indicates
that valid data is being transferred over the upper half of the system data bus.
Use BHE#, in conjunction with A0, to determine which memory byte is being
transferred over the system bus:
BHE#
0
0
1
BHE# is multiplexed with WRH#.
†
Bus Request
This active-low output signal is asserted during a hold cycle when the bus con-
troller has a pending external memory cycle. When the bus-hold protocol is
enabled (WSR.7 is set), the P2.3/BREQ# pin can function only as BREQ#,
regardless of the configuration selected through the port configuration registers
(P2_MODE, P2_DIR, and P2_REG). An attempt to change the pin configuration
is ignored until the bus-hold protocol is disabled (WSR.7 is cleared).
BREQ# is multiplexed with P2.3.
Clock Output
Output of the internal clock generator. The CLKOUT frequency is ½ the internal
operating frequency (f). CLKOUT has a 50% duty cycle.
CLKOUT is multiplexed with P2.7.
Chip-select Lines 0–5
The active-low output CS x # is asserted during an external memory cycle when
the address to be accessed is in the range programmed for chip select x . If the
external memory address is outside the range assigned to the six chip selects,
no chip-select output is asserted and the bus configuration defaults to the CS5#
values.
Immediately following reset, CS0# is automatically assigned to the range
FF2000–FF20FFH (F2000–F20FFH if external).
CS5:0# is multiplexed with P3.5:0.
External Access
This active-low input signal determines whether memory accesses to special
purpose and program memory partitions (FF2000–FFDFFFH) are directed to
internal or external memory. These memory accesses are directed to internal
memory if EA# is deasserted and to external memory if EA# is asserted. For an
access to any other memory location, the value of EA# is irrelevant.
EA# is not latched and can be switched dynamically during normal operating
mode. Be sure to thoroughly consider the issues, such as different access times
for internal and external memory, before using this dynamic switching capability.
Always connect EA# to V
nonvolatile memory.
The chip configuration register 0 (CCR0) determines whether this pin func-
tions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects
WRH#.
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Signal Descriptions (Continued)
A0
0
1
0
Byte(s) Accessed
both bytes
high byte only
low byte only
†
SS
when using a microcontroller that has no internal
Description
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