80C196NU Intel Corporation, 80C196NU Datasheet - Page 18

• Manufacturer Part Number: 80C196NU
• Description: COMMERCIAL CHMOS MICROCONTROLLER
• Manufacturer: Intel Corporation

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8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
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EPA3:0
EPORT.3:0
EXTINT3:0
HLDA#
HOLD#
INST
Name
Type
I/O
I/O
O
O
I
I
Event Processor Array (EPA) Input/Output pins
These are the high-speed input/output pins for the EPA capture/compare chan-
nels. For high-speed PWM applications, the outputs of two EPA channels (either
EPA0 and EPA1 or EPA2 and EPA3) can be remapped to produce a PWM wave-
form on a shared output pin.
EPA3:0 are multiplexed with P1.3:0.
Extended Addressing Port
This is a standard, 4-bit, bidirectional I/O port.
EPORT.3:0 are multiplexed with A19:16.
External Interrupts
In normal operating mode, a rising edge on EXTINT x sets the EXTINT x inter-
rupt pending bit. EXTINT x is sampled during phase 2 (CLKOUT high). The min-
imum high time is one state time.
In standby and powerdown modes, asserting the EXTINT x signal for at least 50
ns causes the device to resume normal operation. The interrupt need not be
enabled, but the pin must be configured as a special-function input. If the
EXTINT x interrupt is enabled, the CPU executes the interrupt service routine.
Otherwise, the CPU executes the instruction that immediately follows the com-
mand that invoked the power-saving mode.
In idle mode, asserting any enabled interrupt causes the device to resume nor-
mal operation.
EXTINT0 is multiplexed with P2.2, EXTINT1 is multiplexed with P2.4, EXTINT2
is multiplexed with P3.6, and EXTINT3 is multiplexed with P3.7.
Bus Hold Acknowledge
This active-low output indicates that the CPU has released the bus as the result
of an external device asserting HOLD#. When the bus-hold protocol is enabled
(WSR.7 is set), the P2.6/HLDA# pin can function only as HLDA#, regardless of
the configuration selected through the port configuration registers (P2_MODE,
P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored
until the bus-hold protocol is disabled (WSR.7 is cleared).
HLDA# is multiplexed with P2.6.
Bus Hold Request
An external device uses this active-low input signal to request control of the bus.
When the bus-hold protocol is enabled (WSR.7 is set), the P2.5/HOLD# pin can
function only as HOLD#, regardless of the configuration selected through the
port configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to
change the pin configuration is ignored until the bus-hold protocol is disabled
(WSR.7 is cleared).
HOLD# is multiplexed with P2.5.
Instruction Fetch
This active-high output signal is valid only during external memory bus cycles.
When high, INST indicates that an instruction is being fetched from external
memory. The signal remains high during the entire bus cycle of an external
instruction fetch. INST is low for data accesses, including interrupt vector
fetches and chip configuration byte reads. INST is low during internal memory
fetches.
Table 8. Signal Descriptions (Continued)
Description
PRELIMINARY