SCC2692 Philips, SCC2692 Datasheet

no-image

SCC2692

Manufacturer Part Number
SCC2692
Description
Dual asynchronous receiver/transmitter DUART
Manufacturer
Philips
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SCC2692AA1N28
Manufacturer:
NDK
Quantity:
2
Part Number:
SCC2692AC-40
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Part Number:
SCC2692AC1
Manufacturer:
LINEAR
Quantity:
2
Part Number:
SCC2692AC1A
Manufacturer:
SIE
Quantity:
5 510
Part Number:
SCC2692AC1A
Manufacturer:
NICHICON
Quantity:
5 510
Part Number:
SCC2692AC1A44
Manufacturer:
IXYS
Quantity:
670
Part Number:
SCC2692AC1A44
Manufacturer:
NXP
Quantity:
1 071
Part Number:
SCC2692AC1A44
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Part Number:
SCC2692AC1A44
Manufacturer:
PHILIPS
Quantity:
14 768
Part Number:
SCC2692AC1A44,512
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
SCC2692AC1A44G
Manufacturer:
PHILIPS
Quantity:
18 105
Part Number:
SCC2692AC1B44,528
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
SCC2692AC1B44,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
SCC2692AC1B44,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips
Semiconductors
Product specification
Supersedes data of 1998 Feb 19
IC19 Data Handbook
SCC2692
Dual asynchronous receiver/transmitter
(DUART)
INTEGRATED CIRCUITS
1998 Sep 04

Related parts for SCC2692

SCC2692 Summary of contents

Page 1

... SCC2692 Dual asynchronous receiver/transmitter (DUART) Product specification Supersedes data of 1998 Feb 19 IC19 Data Handbook Philips Semiconductors INTEGRATED CIRCUITS 1998 Sep 04 ...

Page 2

... In addition, a flow control capability is provided to disable a remote DUART transmitter when the receiver buffer is full. Also provided on the SCC2692 are a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control ...

Page 3

... OP1 15 OP3 16 OP5 17 OP7 GND Figure 1. Pin Configurations PARAMETER DIP28 DIP40 PLCC44 PQFP44 DIP28 DIP40 PLCC44 PQFP44 3 Product specification SCC2692 PQFP TOP VIEW PIN/FUNCTION PIN/FUNCTION N/C 24 INTRN 2 IP0 ...

Page 4

... RECEIVE HOLDING REG (3) RECEIVE SHIFT REGISTER MRA1, 2 CRA SRA CHANNEL B (AS ABOVE) INPUT PORT CHANGE OF STATE DETECTORS (4) IPCR ACR OUTPUT PORT FUNCTION SELECT LOGIC OPCR OPR Figure 2. Block Diagram 4 Product specification SCC2692 TxDA RxDA TxDB RxDB 7 IP0-IP6 8 OP0-OP7 V CC GND SD00132 ...

Page 5

... CC pull-up device supplying current. CC pull-up device supplying current. CC pull-up device supplying current. CC pull-up device supplying current. CC pull-up device supplying current Product specification SCC2692 pull-up CC ...

Page 6

... CMOS input levels CMOS input levels -0.2V and V CC PARAMETER PARAMETER Product specification SCC2692 LIMITS UNIT UNIT Min Typ Max 0.8 V 2.0 V 2 - ...

Page 7

... Minimum frequencies are not tested but are guaranteed by design. 9. 325ns maximum for T > 10. Operation to 0MHz is assured by design. Minimum test frequency is 2.0MHz. Crystal frequencies MHz. 1998 Sep PARAMETER PARAMETER 7 Product specification SCC2692 LIMITS UNIT UNIT 3 Min Typ Max ...

Page 8

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) BLOCK DIAGRAM The SCC2692 DUART consists of the following eight major sections: data bus buffer, operation control, interrupt control, timing, communications Channels A and B, input port and output port. Refer to the Block Diagram. Data Bus Buffer The data bus buffer provides the interface between the external and internal data buses ...

Page 9

... OPERATION Transmitter The SCC2692 is conditioned to transmit data when the transmitter is enabled through the command register. The SCC2692 indicates to the CPU that it is ready to accept a character by setting the TxRDY bit in the status register. This condition can be programmed to generate an interrupt request at OP6 or OP7 and INTRN ...

Page 10

... FIFO while the A/D bit is loaded into the status FIFO position normally used for parity error (SRA[5] or SRB[5]). Framing error, overrun error, and break detect operate normally whether or not the receive is enabled. 10 Product specification SCC2692 ...

Page 11

... CSRA CSRA RECEIVER CLOCK SELECT CSRB CSRB See Text * See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B” in application notes elsewhere in this publication BIT 7 BIT 6 MISCELLANEOUS COMMANDS CRA ...

Page 12

... INT INT INT 0 = Off 0 = Off 0 = Off BIT 5 BIT 4 BIT 3 C/T[13] C/T[12] C/T[11] BIT 5 BIT 4 BIT 3 C/T[5] C/T[4] C/T[3] 12 Product specification SCC2692 BIT 2 BIT 1 BIT 0 TxRDY FFULL RxRDY Yes 1 = Yes 1 = Yes BIT 2 BIT 1 BIT 0 OP3 OP2 00 = OPR[ TxCA(16X TxCA(1X RxCA(1X) BIT 2 ...

Page 13

... The TxDA output is held High. 4. The RxDA input is ignored. 5. The transmitter must be enabled, but the receiver need not be enabled. 6. CPU to transmitter and receiver communications continue nor- mally. The second diagnostic mode is the remote loopback mode, selected by MR2A[7:6] = 11. In this mode: 13 Product specification SCC2692 ...

Page 14

... If an external 1X clock is used for the transmitter, MR2A[ selects one stop bit and MR2A[ selects two stop bits to be transmitted. 14 Product specification SCC2692 ...

Page 15

... C/T to the regular START/STOP counter commands. It does IP6-1X not stop the counter, or clear any pending interrupts. After disabling the timeout mode, a ‘Stop Counter’ command should be issued to reset the ISR(3) bit. 1101 Not used. 15 Product specification SCC2692 ACR[ ACR[ IP5-16X IP5-16X IP5-1X IP5-1X ...

Page 16

... CPU reads the RHR, if after this read there are not more characters still in the FIFO. SRB – Channel B Status Register The bit definitions for this register are identical to the bit definitions for SRA, except that all status applies to the Channel B receiver and transmitter and the corresponding inputs and outputs. 16 Product specification SCC2692 ...

Page 17

... If a bit is in the ‘on’ state the setting of the corresponding bit in the IPCR will also result in the setting of ISR[7], which results in the generation of an interrupt output if IMR[ bit is in the ‘off’ state, the setting of that bit in the IPCR has no effect on ISR[7]. 17 Product specification SCC2692 ERROR (%) 0 0 -0.069 0.059 ...

Page 18

... CTUR/CTLR registers is H‘0002’. Note that these registers are write-only and cannot be read by the CPU. In the timer (programmable divider) mode, the C/T generates a square wave with a period of twice the value (in clock periods) of the CTUR and CTLR. The waveform so generated is often used for a 18 Product specification SCC2692 ...

Page 19

... However, note that a subsequent start counter command will cause the counter to begin a new count cycle using the values in CTUR and CTLR. t RES SD00133 Figure 3. Reset Timing 19 Product specification SCC2692 ...

Page 20

... INPUT PINS WRN OP0–OP7 (b) OUTPUT PINS 1998 Sep RWD NOT VALID FLOAT VALID t RWD VALID Figure 4. Bus Timing OLD DATA Figure 5. Port Timing 20 Product specification SCC2692 SD00134 NEW DATA SD00135 ...

Page 21

... WHEN TTL DEVICE t CTC SCC2698B = 20PF X1 3pF 50 TO 150 K X2 4pF TYPICAL CRYSTAL SPECIFICATION 2 – 4MHZ ): 12 – 32pF L PARALLEL RESONANT, FUNDAMENTAL MODE Figure 7. Clock Timing 21 Product specification SCC2692 V +0. +0. SD00136 + INTERNAL CLOCK DRIVERS SD00137 ...

Page 22

... Timing shown for MR2( 1998 Sep 04 1 BIT TIME ( CLOCKS) t TXD t TCS Figure 8. Transmitter External t t RXS RXH Figure 9. Receive External Clock D2 D3 BREAK D3 START D4 STOP BREAK BREAK Figure 10. Transmitter Timing 22 Product specification SCC2692 SD00138 SD00139 WILL D6 NOT BE TRANSMITTED OPR( SD00140 ...

Page 23

... BE LOST Figure 11. Receiver Timing BIT 9 BIT MR1( ADD#2 BIT 9 BIT STATUS DATA ADD#1 D0 Figure 12. Wake-Up Mode 23 Product specification SCC2692 D6, D7, D8 WILL BE LOST STATUS DATA STATUS DATA RESET BY COMMAND SD00141 BIT 9 ADD#2 1 BIT 9 BIT 9 ADD STATUS DATA ...

Page 24

... When in the BRG test mode, the baud rates change as shown to the left. This change affects all receivers and transmitters on the DUART. See “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681 and SCC2698B” in application notes elsewhere in this publication The test mode at address H‘A’ changes all transmitters and receivers to the 1x mode and connects the output ports to some internal nodes ...

Page 25

... Time out periods can be enabled using the counter/timer in the SCC2691, SCC2692, SCC2698B and SC68692 products. This monitoring can indicate a potential start bit corruption problem. ...

Page 26

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) DIP40: plastic dual in-line package; 40 leads (600 mil) 1998 Sep 04 26 Product specification SCC2692 SOT129-1 ...

Page 27

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) DIP28: plastic dual in-line package; 28 leads (600 mil) 1998 Sep 04 27 Product specification SCC2692 SOT117-1 ...

Page 28

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) PLCC44: plastic leaded chip carrier; 44 leads 1998 Sep 04 28 Product specification SCC2692 SOT187-2 ...

Page 29

... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 1.75 mm 1998 Sep 04 29 Product specification SCC2692 SOT307-2 ...

Page 30

... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors 1998 Sep 04 [1] Copyright Philips Electronics North America Corporation 1998 Document order number: 30 Product specification SCC2692 All rights reserved. Printed in U.S.A. Date of release: 09-98 9397 750 04359 ...

Related keywords