IDT71V2556S Integrated Device Technology, IDT71V2556S Datasheet - Page 13

• Manufacturer Part Number: IDT71V2556S
• Description: 128k X 36, 256k X 18 3.3v Synchronous Zbt Srams 2.5v I/o, Burst Counter Pipelined Outputs
• Manufacturer: Integrated Device Technology

Read Operation with Clock Enable Used
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE
Write Operation with Clock Enable Used
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Cycle
Cycle
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n
n
Address
Address
A
A
A
A
A
A
A
A
A
A
X
X
X
X
X
X
0
2
3
4
0
2
3
4
1
1
1
1
= L, CE
= L, CE
R/W
R/W
X
X
X
X
X
X
H
H
H
H
H
L
L
L
L
L
2
2
= L and CE
= L and CE
ADV/LD
ADV/LD
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
2
2
= H. CE = H is defined as CE
= H. CE = H is defined as CE
CE
CE
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
(2)
(2)
CEN
CEN
L
H
L
H
H
L
L
L
L
H
L
H
H
L
L
L
BWx
BWx
6.42
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
13
1
1
= H, CE
= H, CE
OE
OE
(1)
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
(1)
2
2
= H or CE
= H or CE
I/O
I/O
Q
Q
Q
Q
Q
D
D
D
X
X
X
X
X
X
X
X
0
0
0
2
0
1
2
1
2
2
Commercial and Industrial Temperature Ranges
= L.
= L.
Comments
Clock n+1 Ignored
Clock Valid
Clock Ignored. Data Q
Clock Ignored. Data Q
Comments
Clock n+1 Ignored.
Clock Valid.
Clock Ignored.
Clock Ignored.
Address and Control meet setup
Address A
Address A
Address A
Address and Control meet setup.
Write Data D
Write Data D
Write Data D
0
1
2
Read out (bus trans.)
Read out (bus trans.)
Read out (bus trans.)
0
1
2
0
0
is on the bus.
is on the bus.
4875 tbl 17
4875 tbl 18