T6828 ATMEL Corporation, T6828 Datasheet - Page 4

• Manufacturer Part Number: T6828
• Description: (T6818 / T6828) Triple Halfbridge DMOS OUTPUT DRIVER
• Manufacturer: ATMEL Corporation

Functional Description
Serial Interface
Figure 3. Data Transfer
4
CLK
DO
CS
DI
T6818/T6828
0
SRR
TP
1
S1L
LS1
2
S1H
HS1
3
S2L
LS2
Data transfer starts with the falling edge of the CS signal. Data must appear at DI syn-
chronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0,
SRR) has to be transferred first. Execution of new input data is enabled on the rising
edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is
enabled on the falling edge of CS. Output data will change their state with the rising
edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is
transferred first.
Table 1. Input Data Protocol
Bit
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
4
S2H
HS2
Input Register
5
S3L
LS3
SRR
OCS
HS1
HS2
HS3
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
LS1
LS2
LS3
6
S3H
HS3
7
n. u.
n. u.
Function
Status register reset (high = reset; the bits PSF, OPL and SCD in
the output data register are set to low)
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
See LS1
See HS1
See LS1
See HS1
Not used
Not used
Not used
Not used
Not used
Not used
Overcurrent shutdown (high = overcurrent shutdown is active)
Not used
Not used
8
n. u.
n. u.
9
n. u.
n. u.
10
n. u.
n. u.
11
n. u.
n. u.
12
n. u.
n. u.
13
SCD
OCS
14
OPL
n. u.
4530E–BCD–07/04
15
PSF
n. u.