HV302 Supertex Inc, HV302 Datasheet - Page 9

• Manufacturer Part Number: HV302
• Description: Sequencing Hotswap Controllers
• Manufacturer: Supertex Inc

Design Information -
Start up Overload Protection
Start up must be achieved within a nominal 100ms as indicated by
the PWRGD-A pin transition to the active state or the circuit will
reset and an Auto-Retry will initiate. If there is an output overload
or short circuit during start up, the circuit will be in current limit
mode for the 100ms time limit (in servo mode).
capacitor mode the circuit breaker will shutdown the MOSFET
before 100ms.
Circuit Breaker Delay
The circuit breaker will trip in less than 5 s when the voltage on
the SENSE pin reaches a nominal 100mV. A resistor in series with
the SENSE pin and a capacitor connected between the SENSE
and VEE pins may be added to delay the rate of voltage rise on the
SENSE pin, thus permitting a current overshoot and delaying
Circuit Breaker activation. This method is particularly useful when
operating in Feedback Capacitor Mode. However, in Servo Mode
operation it will result in a current limit leading edge overshoot.
Auto-Retry and Auto-Retry Disable
The Auto-Retry delay time is directly proportional to the
capacitance at the RAMP pin. Auto-Retry sequence is activated
whenever the 100ms timeout is reached during start up or the
Circuit Breaker is tripped.
Auto-Retry can be approximated as a 555-timer with 2.5 A charge
up and charge down currents through 8V, to a count of 256.
Therefore,
For C
Due to the 2.5 A maximum charge current a resistor which draws
more than 2.5 A below 8V will disable Auto-Retry. Try to keep this
resistor as big as possible, e.g. 2.5M . For most MOSFETs with
maximum Vt of 4V, this will vary the 10 A RAMP current source by
only
PWRGD Flag Delay Programming
Shortly after current limiting ends, PWRGD-A becomes active
indicating successful completion of the Hotswap operation.
PWRGD-B will change to an active state a programmed delay time
after PWRGD-A went active, PWRGD-C will change to an active
state a programmed delay time after PWRGD-B went active and
PWRGD-D will change to an active state a programmed delay time
after PWRGD-C went active.
respective TB, TC and TD pins to V
delay times between the PWRGD flags sequentially going active.
2
RAMP
5 .
4
M
V
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: [phone] Fax: [phone] www.supertex.com
= 10nF
t
t
Auto
Auto
1
Re
Re
6 .
try
try
A
2
2
2
2
8
8
5 .
5 .
256
A
256
A
continued
10
C
Resistors connected from the
RAMP
EE
nF
pin are used to program the
16
4 .
s
In feedback
9
The following waveforms demonstrate the sequencing of the
PWRGD flags. These results were obtained with R
= 60k and R
The value of the resistors determines the capacitor charging and
discharging current of a triangle wave oscillator. The oscillator
output is fed to an 8-bit counter to generate the desired time delay.
The respective delay time is defined by the following equation:
and
Where
Combining the above two equations and solving for R
For a delay time of 200ms we get:
For a delay time of 5ms we get:
t
C
V
I
Vbg = 1.2V (Internal Band Gap Reference)
R
I
t
R
R
R
R
TX
CD
CD
TX
PP
OSC
TX
TX
TX
TX
TX
= Delay Time between respective PWRGD flags
= Charge and Discharge current of oscillator
TD
= 8.2V (Peak-to-Peak voltage swing of oscillator)
= Programming resistor at TB, TC or TD pin
= 120pF (Internal oscillator capacitor)
4
255
= 3k
0
V
2040
R
0
0
6 .
bg
6 .
6 .
TX
Rev. D
B
10
2
10
10
bg
C
6
I
6
6
CD
C
PP
t
OSC
TX
t
TX
200
5
V
PP
10
V
PP
10
3
2040
3
k 3
1
120
2 .
HV302 / HV312
120
V
k
pF
t
TX
TB
8
2 .
= 120k , R
TX
04/17/02
V
yields:
TC