TDA8841-N2 Philips Semiconductors, TDA8841-N2 Datasheet - Page 43

• Manufacturer Part Number: TDA8841-N2
• Description: I2C-bus controlled PAL/NTSC/SECAM TV processors
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Notes
1. On set AGC.
2. This parameter is not tested during production and is just given as application information for the designer of the
3. Loop bandwidth BL = 60 kHz (natural frequency fN = 15 kHz; damping factor d = 2; calculated with top sync level as
4. The IF-PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a
5. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
6. Measured at 10 mV (RMS) top sync input signal.
7. So called projected zero point, i.e. with switched demodulator.
8. Measured in accordance with the test line given in Fig.14. For the differential phase test the peak white setting is
December 16, 1997
BEAM CURRENT LIMITING
C.7.4
C.7.5
C.7.6
C.7.7
C.7.8
BLUE STRETCH
C.8.1
C.8.2
C.8.3
I
B.1.1
B.1.2
B.1.3
B.1.4
B.1.5
B.1.6
2
NUMBER
C-BUS CONTROL INPUT/OUTPUT (SDA/SCL)
I
processors
2
television receiver.
FPLL input signal level).
digital control circuit which uses the X-tal frequency of the colour decoder as a reference. The required IF frequency
for the various standards is set via the I
resulting IF frequency is very accurate with a deviation from the nominal value of less than 25 kHz.
batches which are made in the pilot production period.
reduced to 87%.
The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and
smallest value relative to the subcarrier amplitude at blanking level.
The phase difference is defined as the difference in degrees between the largest and smallest phase angle.
C-bus controlled PAL/NTSC/SECAM TV
;
voltage difference for full
brightness reduction
internal bias voltage
detection level vertical guard
minimum input current to
activate the guard circuit
maximum allowable current
decrease of small signal gain for
the red and green channel
decrease of small signal gain for
the red channel
decrease of small signal gain for
the green channel
input voltage level
low-level input voltage
high-level input voltage
low-level input current
high-level input current
low-level output voltage
NOTE
53
PARAMETER
(
CONTINUED
)
2
C-bus (IFA-IFC bits in sub-address 15H). When the system is locked the
BLS = 1
EBS = 1
EBS = 1
V
V
SDA, I
i
i
= 0 V
= 5.5 V
L
CONDITIONS
= 3 mA
43
0
3.5
TDA884X/5X-N2 series
MIN.
Tentative Device Specification
1
3.3
3.65
100
1
14
22
8
TYP.
5.5
1.5
-10
10
0.4
MAX.
V
V
V
mA
%
%
%
V
V
V
V
UNIT
A
A
A