NCP1575 ON Semiconductor, NCP1575 Datasheet - Page 11
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NCP1575
Manufacturer Part Number
NCP1575
Description
Low Voltage Synchronous Buck Controller
Manufacturer
ON Semiconductor
Datasheet
1.NCP1575.pdf
(16 pages)
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Normal Operation
remains approximately constant as the V
maintains the regulated output voltage under steady state
conditions. Variations in supply line or output load conditions
will result in changes in duty cycle to maintain regulation.
Input Supplies
supply is available along with a lower voltage supply. Often
the lower voltage supply is 5 V, but it can be any voltage less
than the 12 V supply minus the required gate drive voltage
of the top MOSFET. The greater the difference between the
two voltages, the better the efficiency due to increasing V
available to turn on the upper MOSFET. In order to maintain
power supply stability, the lower supply voltage should be
at least 1.5 times the desired voltage.
to convert power in a “12 V only” application. This circuit
is illustrated in Figure 1. Note that in all cases, the maximum
supply voltage specification of 20 V must not be exceeded.
Gate Charge Effect on Switching Times
an important effect on the switching times of the FETs. A
finite amount of time is required to charge the effective
capacitor seen at the gate of the FET. Therefore, the rise and
fall times rise linearly with increased capacitive loading.
Transient Response
transient response to any variations in input voltage and
output current. Pulse−by−pulse adjustment of duty cycle is
provided to quickly ramp the inductor current to the required
level. Since the inductor current cannot be changed
instantaneously, regulation is maintained by the output
capacitors during the time required to slew the inductor
current. For better transient response, several high
frequency and bulk output capacitors are usually used.
Overvoltage Protection
normal operation of the V
additional external components. The control loop responds
0.465 V
During normal operation, the duty cycle of the gate drivers
The NCP1575 can be used in applications where a 12 V
Adding a few additional components allows the NCP1575
When using the onboard gate drivers, the gate charge has
The 200 ns reaction time of the control loop provides fast
Overvoltage protection is provided as a result of the
8.5 V
UVLO
Figure 21. Idealized Waveforms
STARTUP
2
control method and requires no
t
S
NORMAL OPERATION
2
control loop
V
V
V
GATE(H)
IN
COMP
FB
http://onsemi.com
GS
NCP1575
11
to an overvoltage condition within 200 ns, turning off the
upper MOSFET and disconnecting the regulator from its
input voltage. This results in a crowbar action to clamp the
output voltage, preventing damage to the load. The regulator
remains in this state until the overvoltage condition ceases.
Shutdown
lower threshold of the UVLO comparator, a fault latch is set.
The fault latch provides a signal that forces both GATE(H)
low and GATE(L) high, producing a low−impedance current
sink to ground at the converter switch node. At the same
time, the latch also turns on a transistor which pulls down on
the COMP pin, quickly discharging the external capacitor,
and allowing COMP to fall.
Choosing the V
divider is used to set the output voltage.
that the V
negligible effect on the output voltage. Solve the equation
above for the value of R1.
Choosing the Oscillator Frequency
at the factory. The NCP1575 will operate at this frequency
without the addition of any external components. However,
the oscillator is user−programmable with a single resistor.
This resistor is connected between the R
Adding this resistor will raise the frequency above 200 kHz.
A graph of oscillator frequency vs. R
provided in the typical operating characteristics section of
this data sheet.
Selection of the Output Capacitors
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are their Equivalent
When the input voltage connected to V
The NCP1575 has an internal 0.98 V reference. A resistor
The formula to set the output voltage is
Arbitrarily choose a value of R2 that is sufficiently low
The NCP1575 has an oscillator that is trimmed to 200 kHz
These components must be selected and placed carefully
FB
V OUT + (R1 R2 ) 1) < (0.98 V)
bias current (typically 50 nA) will have
V
OUT
FB
CONVERTER DESIGN
Resistor Divider Values
Figure 22.
R1
R2
V
OSC
OUT
CC
OSC
falls through the
pin and ground.
resistance is