STLVDS385 ST Microelectronics, STLVDS385 Datasheet
STLVDS385
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STLVDS385 Summary of contents
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... PLL REQUIRES NO EXTERNAL COMPONENTS COMPATIBLE WITH TIA/EIA -644 LVDS STANDARD DESCRIPTION The STLVDS385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS ORDERING CODES ...
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... STLVDS385 PIN CONFIGURATION PIN DESCRIPTION PlN N° SYMBOL 10, 11, 12, 14, 15, 16, 18, 19, 20, 22, 23, 24, 25, 27, 28, 30, 50, 51, 52, 54, 55 13, 21 R_FB 31 TxCLKIN 32 PWRDWN 33, 35 PLL GND PLL V 34 36, 43, 49 LVDS GND 37, 41, 45, 47 TxOUT+ 38, 42, 46, 48 ...
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... A Parameter = 3.3V -10 to 70°C unless otherwise noted. Typical CC J Test Conditions I = -18mA CL V =0 GND I STLVDS385 STROBE STATUS Rising edge strobe Falling edge strobe Value -0 -0 0. 0.3) CC Continuous 7 500 ± 300 +150 -65 to +150 Min. ...
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... STLVDS385 LVDS DC SPECIFICATIONS (V referred 25°C) A Symbol Parameter V Differential Output Voltage OD V Change in V between OD OD Complimentary Output States V Offset Voltage (Note Change in V between OS OS Complimentary Output States I Output Short Circuit Current Output Tri-State Current OZ TRANSMITTER SUPPLY CURRENT (V values are referred 25° ...
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... Conditions 0.75 0. MHz -0.25 0 3.32 3.57 6.89 7.14 10.46 10.71 14.04 14.29 17.61 17.86 21.18 21. MHz -0.20 0 2.00 2.20 4.20 4.40 6.39 6.59 8.59 8.79 10.79 10.99 12.99 13. MHz -0.20 0 1.48 1.68 3.16 3.36 4.84 5.04 6.52 6.72 8.20 8.40 9.88 10.08 2 25°C, 3 3. MHz 110 MHz 210 MHz 350 STLVDS385 Max. Unit 1.5 ns 1.5 ns 0.25 ns 3.82 ns 7.39 ns 10.96 ns 14.54 ns 18.11 ns 21.68 ns 0.20 ns 2.40 ns 4.60 ns 6.79 ns 8.99 ns 11.19 ns 13.99 ns 0.20 ns 1.88 ns 3.56 ns 5.24 ns 6.92 ns 8.60 ns 10. 6.3 ns 7.1 ns 150 ps 230 370 10 ms 100 ns 5/14 ...
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... STLVDS385 AC TIMING DIAGRAMS Figure 1 : "Worst Case" Test Pattern (Note 5) 6/14 ...
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... Figure 2 : "16 Grayscale" Test Patter (Notes STLVDS385 7/14 ...
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... STLVDS385 Figure 3 : (Transmitter) LVDS Output Load Figure 4 : (Transmitter) LVDS Transition Time Figure 5 : (Transmitter) Input Clock Transition Time 8/14 ...
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... Figure 6 : (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) Figure 7 : (Transmitter) Clock In to Clock Out Delay STLVDS385 9/14 ...
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... STLVDS385 Figure 8 : (Transmitter) Phase Lock Loop Set Time Figure Parallel TTL Data Inputs Mapped to LVDS Outputs 10/14 ...
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... Figure 10 : Transmitter Power Down Delay Figure 11 : Transmitter LVDS Output Pulse Position Measurement STLVDS385 11/14 ...
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... STLVDS385 DIM. MIN 0. 0.17 c 0.09 D 13.9 E 7. 0˚ PIN 1 IDENTIFICATION 1 12/14 TSSOP56 MECHANICAL DATA mm. TYP MAX. 1.2 0.15 0.9 0.27 0.20 14.1 8.25 6.2 0.5 BSC 8˚ 0. inch MIN. TYP. 0.002 0.035 0.0067 0.0035 0.0079 0.547 0.313 0.236 0.0197 BSC 0˚ 0.020 7065590B MAX. 0.047 ...
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... Tape & Reel TSSOP56 MECHANICAL DATA DIM. MIN 12 8.7 Bo 17.2 Ko 1.4 Po 3.9 P 11.9 mm. TYP MAX. MIN. 330 13.2 0.504 0.795 2.362 30.4 8.9 0.342 17.4 0.677 1.6 0.055 4.1 0.153 12.1 0.468 STLVDS385 inch TYP. MAX. 12.992 0.519 1.197 0.350 0.685 0.063 0.161 0.476 13/14 ...
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... STLVDS385 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...