74ALVC16240 Fairchild Semiconductor, 74ALVC16240 Datasheet
74ALVC16240
Related parts for 74ALVC16240
74ALVC16240 Summary of contents
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... The device is nibble (4-bit) controlled. Each nibble has sep- arate 3-STATE control inputs which can be shorted together for full 16-bit operation. The 74ALVC16240 is designed for low voltage (1.65V to 3.6V) V applications with I/O capability up to 3.6V. CC The 74ALVC16240 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain- ing low CMOS power dissipation ...
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... Connection Diagram Functional Description The 74ALVC16240 contains sixteen inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE outputs are con- Logic Diagram www ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 3) 0. Input Diode Current ( Output Diode Current (I ) ...
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AC Electrical Characteristics Symbol Parameter V CC Min Propagation Delay PHL PLH 1.3 Bus to Bus Output Enable Time 1.3 PZL PZH Output Disable Time 1.3 PLZ PHZ Capacitance Symbol Parameter ...
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AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3.3V 0. FIGURE 2. Waveform for Inverting and ...
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Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...