FLLXT971A Intel, FLLXT971A Datasheet - Page 68
FLLXT971A
Manufacturer Part Number
FLLXT971A
Description
3.3V Dual Speed Fast Ethernet PHY Transceicer
Manufacturer
Intel
Datasheet
1.FLLXT971A.pdf
(90 pages)
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
68
Figure 36. Auto-Negotiation and Fast Link Pulse Timing
Figure 37. Fast Link Pulse Timing
Table 37. Auto-Negotiation and Fast Link Pulse Timing Parameters
Clock/Data pulse width
Clock pulse to Data pulse
Clock pulse to Clock pulse
FLP burst width
FLP burst to FLP burst
Clock/Data pulses per burst
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
TPFOP
TPFOP
testing.
Parameter
Clock Pulse
FLP Burst
t1
t4
Symbol
t2
t1
t2
t3
t4
t5
–
55.5
Min
123
17
t5
–
–
8
Data Pulse
Typ
100
t1
t3
12
–
–
2
–
1
Max
63.8
127
24
33
–
–
FLP Burst
Units
ms
ms
µ s
µ s
ea
ns
Clock Pulse
Rev. Date: August 7, 2002
Test Conditions
Document #: 249414
Revision #: 002
Datasheet
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