LMX2370 National Semiconductor, LMX2370 Datasheet - Page 10

• Manufacturer Part Number: LMX2370
• Description: PLLatinum Dual Frequency Synthesizer for RF Personal Communications
• Manufacturer: National Semiconductor

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Aux_N
Main_N
Divide Ratio
2.0 Programming Description
Note: B-counter divide ratio must be
Notes: A
2.3.2 Main_N Register
If the ADDRESS[1:0] field is set to 1 1, data is transferred from the 22-bit shift register into the Main_N register which sets the
Main PLL’s 18-bit N-counter, prescaler value and power-down bit. The 18-bit N-counter consists of a 5-bit swallow counter,
Main_A_CNTR[4:0], and a 13-bit programmable counter, Main_B_CNTR[12:0]. Serial data format is shown below.
2.3.3 Feedback Divide Ratio (Main B Counter, Auxiliary B Counter)
2.3.4 Swallow Counter Divide Ratio (Main A Counter, Auxiliary A Counter)
Divide Ratio
8,191
3
4
•
<
Most Significant Bit
21
31
Most Significant Bit
21
0
1
•
P,
20
20
B
>
N17
A.
19
0
0
1
19
•
18
18
N16
0
0
1
Main_N4
•
17
17
3.
0
0
1
•
16
16
N15
0
0
1
•
15
15
Main_B_CNTR[12:0]
Aux_B_CNTR[12:0]
14
14
N14
0
0
1
•
SHIFT REGISTER BIT LOCATION
SHIFT REGISTER BIT LOCATION
Main_B_CNTR[12:0] or Aux_B_CNTR[12:0]
Main_N3
(Continued)
13
13
Data Field
Data Field
0
0
1
•
Main_A_CNTR[4:0] or Aux_A_CNTR[4:0]
N13
12
12
0
0
1
•
11
11
10
N12
0
0
1
•
10
10
Main_N2
9
9
N11
0
0
1
•
0
0
1
•
8
8
7
7
N10
0
0
1
•
6
6
Main_A_CNTR[4:0]
Aux_A_CNTR[4:0]
5
5
N9
0
0
1
Main_N1
•
4
4
0
0
1
•
N8
0
0
1
•
3
3
Least Significant Bit
Least Significant Bit
2
2
N7
0
1
1
•
Address Field
Address Field
Main_N0
1
0
1
1
N6
1
0
1
•
0
1
1
•
0
1
N5
0
1
1
1
1
•